Yamaha HTR-6066, Service Manual

Page: 78 / 182

Pin
Function Name
TYPE PULL
Detail of Function
No. (1) (2)
116 AXR0[4]/ AXR2[1]/GP3[4] I/O IPD McASP0 serial data
O IPD McASP2 serial data
117 AXR0[5]/AFSX2/GP3[5] I/O IPD McASP0 serial data
O IPD McASP2 transmit frame sync
118 AXR0[6]/ACLKR2/GP3[6] I/O IPD McASP0 serial data
I/O IPD McASP2 receive bit clock
119 DVDD (I/O supply) PWR 3.3-V I/O supply voltage pins
120 AXR0[7]/GP3[7] I/O IPD McASP0 serial data
121 AXR0[8]/GP3[8] I/O IPU McASP0 serial data
122 UART1_RXD/AXR0[9]/GP3[9] I IPD UART1 receive data
(3) I/O IPD McASP0 serial data
123 UART1_TXD/AXR0[10]/GP3[10] O IPD UART1 transmit data
(3) I/O IPD McASP0 serial data
124 AXR0[11]/ AXR2[0]/GP3[11] I/O IPD McASP0 serial data
O IPD McASP2 serial data
125 AHCLKX0/AHCLKX2/USB_REFCLKIN/GP2[11] I/O IPD McASP0 transmit master clock
O IPD McASP2 transmit master clock
I IPD USB_REFCLKIN. Optional 48 MHz clock input
126 ACLKX0/ECAP0/APWM0/GP2[12] I/O IPD Enhanced capture 0/input or auxiliary PWM 0 output
I/O IPD McASP0 transmit bit clock
127 AFSX0/GP2[13]/BOOT[10] I IPD BOOT[10]
I/O IPD McASP0 transmit frame sync
128 DVDD (I/O supply) PWR 3.3-V I/O supply voltage pins
129 AHCLKR0/GP2[14]/BOOT[11] I IPD BOOT[11]
I/O IPD McASP0 receive master clock
130 ACLKR0/ECAP1/APWM1/GP2[15] I/O IPD Enhanced capture 1/input or auxiliary PWM 1 output
I/O IPD McASP0 receive bit clock
131 AFSR0/GP3[12] I/O IPD McASP0 receive frame sync
132 AMUTE1/EPWMTZ/GP4[14] I/O IPD eHRPWM0 trip zone input
I/O IPD eHRPWM1 trip zone input
I/O IPD eHRPWM2 trip zone input
O IPD McASP1 mute output
133 RSV2 PWR Reserved. For proper device operation, this pin must be tied directly to CVDD
134 USB0_VDDA12 (4) PWR USB0 PHY 1.2-V LDO output for bypass cap
135 USB0_VDDA18 PWR USB0 PHY 1.8-V supply input
136 NC – –
137 USB0_DP A USB0 PHY data plus
138 USB0_DM A USB0 PHY data minus
139 NC – –
140 USB0_VDDA33 PWR USB0 PHY 3.3-V supply
141 PLL0_VDDA PWR PLL analog VDD (1.2-V filtered supply)
142 PLL0_VSSA GND PLL analog VSS (for filter)
143 OSCIN I Oscillator input
144 OSCVSS GND Oscillator ground (for filter only)
145 OSCOUT O Oscillator output
146 RESET I Device reset input
147 CVDD (Core supply) PWR 1.2-V core supply voltage pins
148 RTC_XI I Low-frequency (32-kHz) oscillator receiver for real-time clock
149 RTC_CVDD PWR RTC module core power ( isolated from rest of chip CVDD)
150 TRST I IPD JTAG test reset
151 DVDD (I/O supply) PWR 3.3-V I/O supply voltage pins
152 TMS I IPU JTAG test mode select
153 TDI I IPU JTAG test data input
154 CVDD (Core supply) PWR 1.2-V core supply voltage pins
155 TCK I IPU JTAG test clock
156 TDO O IPD JTAG test data output
157 GP7[14] (5) I/O IPD General-Purpose IO signal
158 DVDD (I/O supply) PWR 3.3-V I/O supply voltage pins
159 CVDD (Core supply) PWR 1.2-V core supply voltage pins
78
RX-V675/HTR-6066/RX-A730/TSR-6750
RX-V675/HTR-6066/
RX-A730/TSR-6750