Pin
No.
I/O
Port Name
Function Name
Related Power Supply
Detail of Function
OFF
ON
101 A13/[A13/D13]/TA2IN/W/P3_5
A[13]
AC
O
B
External bus
102 A12/[A12/D12]/TA2OUT/W/P3_4
A[12]
AC
O
B
External bus
103 P16_3/TXD9
NCPU_SPI_MOSI
NCPU_PON
O
O
Data (master out slave in)
104 P16_2/RXD9
NCPU_SPI_MISO
NCPU_PON
O
I
Data (master in slave out)
105 P16_1/CLK9
NCPU_SPI_SCK
NCPU_PON
O
O
Clock (master out slave in)
106 P16_0/N_CTS9/N_RTS9
NCPU_N_RST
NCPU_PON
O
O
Network microprocessor reset
107 A11/[A11/D11]/TA1IN/V/P3_3
A[11]
AC
O
B
External bus
108 A10/[A10/D10]/TA1OUT/V/P3_2
A[10]
AC
O
B
External bus
109 A9/[A9/D9]/TA3OUT/UD0B/UD1B/P3_1 A[9]
AC
O
B
External bus
110 D20/P12_4
AD_SEL_A
+3.3S_PON
O
O
AD select A
111 D19/N_CTS6/N_RTS6/N_SS6/P12_3
AD_SEL_B
+3.3S_PON
O
O
AD select B
112 D18/RXD6/SCL6/STXD6/P12_2
AD_SEL_C
+3.3S_PON
O
O
AD select C
113 D17/CLK6/P12_1
FPGA_SCK
HDMI_PON
O
O
FPGA clock (at Boot)
114 D16/TXD6/SDA6/SRXD6/P12_0
FPGA_MOSI
HDMI_PON
O
O
FPGA transmission data (at Boot)
115 VCC
VCC
---
116 A8/[A8/D8]/TA0OUT/UD0A/UD1A/P3_0 A[8]
AC
O
B
External bus
117 VSS
VSS
---
118 A7/[A7/D7]/AN2_7/P2_7/TXD10
A[7]
AC
O
B
External bus
119 A6/[A6/D6]/AN2_6/P2_6/RXD10
A[6]
AC
O
B
External bus
120 A5/[A5/D5]/AN2_5/P2_5/CLK10
A[5]
AC
O
B
External bus
121
A4/[A4/D4]/AN2_4/P2_4/N_CTS10/N_
RTS10
A[4]
AC
O
B
External bus
122 A3/[A3/D3]/AN2_3/P2_3/TXD9
A[3]
AC
O
B
External bus
123 A2/[A2/D2]/AN2_2/P2_2/RXD9
A[2]
AC
O
B
External bus
124
A1/[A1/D1]/BC2/[BC2/D1]/AN2_1/P2_1/
CLK9
A[1]
AC
O
B
External bus
125
A0/[A0/D0]/BC0/[BC0/D0]/AN2_0/P2_0/
N_CTS9/N_RTS9
A[0]
AC
O
B
External bus
126 D15/N_INT5/IIO0_7/IIO1_7/P1_7
D[15]
AC
I
B
External bus
127 D14/N_INT4/IIO0_6/IIO1_6/P1_6
D[14]
AC
I
B
External bus
128 D13/N_INT3/IIO0_5/IIO1_5/P1_5
D[13]
AC
I
B
External bus
129 D12/IIO0_4/IIO1_4/P1_4
D[12]
AC
I
B
External bus
130 D11/IIO0_3/IIO1_3/P1_3
D[11]
AC
I
B
External bus
131 D10/IIO0_2/IIO1_2/P1_2
D[10]
AC
I
B
External bus
132 D9/IIO0_1/IIO1_1/P1_1
D[9]
AC
I
B
External bus
133 IIO0_0/IIO1_0/D8/P1_0
D[8]
AC
I
B
External bus
134 AN0_7/D7/P0_7
D[7]
AC
I
B
External bus
135 AN0_6/D6/P0_6
D[6]
AC
I
B
External bus
136 AN0_5/D5/P0_5
D[5]
AC
I
B
External bus
137 AN0_4/D4/P0_4
D[4]
AC
I
B
External bus
138 P19_1
FPGA_N_CFG
HDMI_PON
O
O
FPGA nCONF
139 WR3/BC3/P11_4
FPGA_N_STA
HDMI_PON
I
I
FPGA nSTATUS
140 P19_0
FPGA_CDONE
HDMI_PON
I
I
FPGA CONF DONE
141
IIO1_3/N_RTS8/N_CTS8/WR2/CS3/
P11_3
DIAG_CHECK
AC
O
O
Diag inspection result output / OK=High, NG=Low
142 IIO1_2/RXD8/CS2/P11_2
NDAC_N_MT
DSP_PON
O
O
Net zone DAC mute
143 IIO1_1/CLK8/CS1/P11_1
SPRY_Z2&FP
PRY
O
O
SP relay zone 2 and front presence
144 IIO1_0/TXD8/CS0/P11_0
NCPU_SPI_N_CS
NCPU_PON
O
O
Network microprocessor SPI chip select
145 P18_7
HPRY
PRY
O
O
HP relay
146 P18_6
MT_N_Z2
+3.3S_PON
O
O
Mute zone2 (line out)
147 P18_5
SPRY_SB&BA
PRY
O
O
SP relay surround back and Bi-Amp
148 P18_4
MT_N_5CH
+3.3S_PON
O
O
Mute 5ch (L, C, R, SRL, SRR preout/main in)
149 P18_3
MT_N_SW
+3.3S_PON
O
O
Mute subwoofer (Preout)
150 P18_2
MT_N_SB
+3.3S_PON
O
O
Mute SB/BA/Z2/FP (Preout/Main in)
151 AN0_3/D3/P0_3
D[3]
AC
I
B
External bus
152 AN0_2/D2/P0_2
D[2]
AC
I
B
External bus
153 AN0_1/D1/P0_1
D[1]
AC
I
B
External bus
154 AN0_0/D0/P0_0
D[0]
AC
I
B
External bus
90
RX-V675/HTR-6066/RX-A730/TSR-6750
RX-V675/HTR-6066/
RX-A730/TSR-6750
Summary of Contents for HTR-6066
Page 126: ...MEMO MEMO RX V675 HTR 6066 RX A730 TSR 6750 126 ...
Page 167: ...167 RX V675 HTR 6066 RX A730 TSR 6750 RX V675 HTR 6066 RX A730 TSR 6750 ADVANCED SETUP ...
Page 168: ...168 RX V675 HTR 6066 RX A730 TSR 6750 RX V675 HTR 6066 RX A730 TSR 6750 ...
Page 181: ...181 RX V675 HTR 6066 RX A730 TSR 6750 RX V675 HTR 6066 RX A730 TSR 6750 MEMO ...
Page 182: ...RX V675 HTR 6066 RX A730 TSR 6750 ...
