Pin
No.
Port Name
Function Name
(P.C.B.)
I/O
Detail of Function
POWER
ON
OFF
129 D12/IIO0_4/IIO1_4/P1_4
D[12]
B
I
External b
u
s
130 D11/IIO0_3/IIO1_3/P1_3
D[11]
B
I
External b
u
s
131 D10/IIO0_2/IIO1_2/P1_2
D[10]
B
I
External b
u
s
132 D9/IIO0_1/IIO1_1/P1_1
D[9]
B
I
External b
u
s
133 IIO0_0/IIO1_0/D8/P1_0
D[8]
B
I
External b
u
s
134 AN0_7/D7/P0_7
D[7]
B
I
External b
u
s
135 AN0_6/D6/P0_6
D[6]
B
I
External b
u
s
136 AN0_5/D5/P0_5
D[5]
B
I
External b
u
s
137 AN0_4/D4/P0_4
D[4]
B
I
External b
u
s
138 P19_1
SV_DET
I
I
S-video detect
139 WR3/BC3/P11_4
EEP_N_CS
O
O
EEPROM chip select
140 P19_0
HP_N_DET
I
O
Headphone detection
141
IIO1_3/N_RTS8/N_CTS8/WR2/
CS3/P11_3
FPGA_N_CS
B
O
External b
u
s
142 IIO1_2/RXD8/CS2/P11_2
EEP_MISO
I
O
EEPROM reception data
143 IIO1_1/CLK8/CS1/P11_1
EX_CLK
O
O
FLD/EEPROM comm
u
nication clock
144 IIO1_0/TXD8/CS0/P11_0
EX_MOSI
O
O
FLD/EEPROM transmission data
145 P18_7
(no
u
se)
O
O
Unconnected
146 P18_6
VDEC_N_RST
O
O
Video decoder reset
147 P18_5
(no
u
se)
O
O
Unconnected
148 P18_4
DAC_N_CS
O
O
DAC chip select
149 P18_3
DIR_N_CS
O
O
DIR chip select
150 P18_2
F_HEQ_CE
O
O
Front HDMI EQ chip enable
151 AN0_3/D3/P0_3
D[3]
B
I
External b
u
s
152 AN0_2/D2/P0_2
D[2]
B
I
External b
u
s
153 AN0_1/D1/P0_1
D[1]
B
I
External b
u
s
154 AN0_0/D0/P0_0
D[0]
B
I
External b
u
s
155
IIO0_7/N_RTS6/N_CTS6/N_SS6/
AN15_7/P15_7
PS1_PRT
I
I
Power s
u
pply protection 1
156 IIO0_6/CLK6/AN15_6/P15_6
PS2_PRT
I
I
Power s
u
pply protection 2
157
IIO0_5/RXD6/SCL6/STXD6/
AN15_5/P15_5
DOCK1_ID
I
I
Dock1 ID detection
158
IIO0_4/TXD6/SDA6/SRXD6/
AN15_4/P15_4
THM2
I
O
Temperat
u
re detection 2
159
IIO0_3/N_RTS7/N_CTS7/AN15_3/
P15_3
THM1
I
O
Temperat
u
re detection 1
160 IIO0_2/RXD7/AN15_2/P15_2
DSP_MISO
I
I
DSP/DIR/DAC reception data
161 IIO0_1/CLK7/AN15_1/P15_1
DSP_CLK
O
O
DSP/DIR/DAC comm
u
nication clock
162 VSS
VSS
---
163 IIO0_0/TXD7/AN15_0/P15_0
DSP_MOSI
O
O
DSP/DIR/DAC transmission data
164 VCC
VCC
---
165 KI3/AN_7/P10_7
AMP_OLV
I
I
Amplifier o
u
tp
u
t level detection
166 KI2/AN_6/P10_6
DC_PRT
I
I
DC protection
167 KI1/AN_5/P10_5
L3_DET
I
I
D terminal L3 detection
168 KI0/AN_4/P10_4
DEST
I
O
Destination discrimination
169 AN_3/P10_3
MODEL
I
O
Model discriminate
170 AN_2/P10_2
KY_AD2
I
O
Key 2
171 AN_1/P10_1
KY_AD1
I
O
Key 1
172 AVSS
AVSS
---
173 AN_0/P10_0
TU_N_RST
O
O
T
u
ner reset
174 VREF
VREF
---
175 AVCC
AVCC
---
176 STXD4/SCL4/RXD4/ADTRG/P9_7 TU_SCL
O
O
T
u
ner I2C clock
68
RX-V471/HTR-4064
RX-V471/HTR-4064
Summary of Contents for HTR-4064
Page 5: ...RX V471 K model RX V471 A model RX V471 B G F models 5 RX V471 HTR 4064 RX V471 HTR 4064 ...
Page 6: ...RX V471 L model RX V471 J model HTR 4064 U model 6 RX V471 HTR 4064 RX V471 HTR 4064 ...
Page 7: ...HTR 4064 G F models HTR 4064 T model HTR 4064 K models 7 RX V471 HTR 4064 RX V471 HTR 4064 ...
Page 124: ... CONFIGURING THE SYSTEM SETTINGS RX V471 HTR 4064 125 ...
Page 125: ... システム設定を変更する RX V471 HTR 4064 126 ...
Page 126: ...127 RX V471 HTR 4064 RX V471 HTR 4064 MEMO ...
Page 127: ...RX V471 HTR 4064 ...
