Pin
No.
Port Name
Function Name
(P.C.B.)
I/O
Detail of Function
POWER
ON
OFF
86
CS1/A22/RXD6/SCL6/STXD6/
P4_6
A[22]
B
O
External b
u
s
87 CS2/A21/CLK6/P4_5
A[21]
B
O
External b
u
s
88
CS3/A20/N_CTS6/N_RTS6/N_
SS6/P4_4
A[20]
B
O
External b
u
s
89
A19/TXD3/SDA3/SRXD3/
OUTC2_0/ISTXD2/IEOUT/P4_3
A[19]
B
O
External b
u
s
90 P11_6
VIDI2C_ON
O
O
I2C line switch to video device
91
A18/RXD3/SCL3/STXD3/ISRXD2/
IEIN/P4_2
A[18]
B
O
External b
u
s
92 P11_5
HTX_AUSEL
O
O
HDMI TX so
u
nd select
93 A17/CLK3/P4_1
A[17]
B
O
External b
u
s
94
A16/N_CTS3/N_RTS3/N_SS3/
P4_0
A[16]
B
O
External b
u
s
95 P16_7/TXD10
DK1_MOSI
O
O
Dock1 transmission data (/Deb
u
g)
96 P16_6/RXD10
DK1_MISO
I
I
Dock1 reception data (/Deb
u
g)
97 P16_5/CLK10
HTX_N_RST
O
O
HDMI TX reset
98 P16_4/N_CTS10/N_RTS10
HRX_N_RST
O
O
HDMI RX reset
99 A15/[A15/D15]/TA4IN/U/P3_7
A[15]
B
O
External b
u
s
100 A14/[A14/D14]/TA4OUT/U/P3_6
A[14]
B
O
External b
u
s
101 A13/[A13/D13]/TA2IN/W/P3_5
A[13]
B
O
External b
u
s
102 A12/[A12/D12]/TA2OUT/W/P3_4
A[12]
B
O
External b
u
s
103 P16_3/TXD9
TXD9
O
O
Spare
104 P16_2/RXD9
RXD9
O
O
Spare
105 P16_1/CLK9
CLK9
O
O
Spare
106 P16_0/N_CTS9/N_RTS9
HEQ_N_RST
O
O
HDMI switcher reset
107 A11/[A11/D11]/TA1IN/V/P3_3
A[11]
B
O
External b
u
s
108 A10/[A10/D10]/TA1OUT/V/P3_2
A[10]
B
O
External b
u
s
109
A9/[A9/D9]/TA3OUT/UD0B/UD1B/
P3_1
A[9]
B
O
External b
u
s
110 D20/P12_4
FPGA_N_CFG
O
O
FPGA nCONF
111
D19/N_CTS6/N_RTS6/N_SS6/
P12_3
FPGA_N_STA
I
I
FPGA nSTATUS
112 D18/RXD6/SCL6/STXD6/P12_2
USB_SCL
O
O
USB I2C clock
113 D17/CLK6/P12_1
FPGA_CDONE
I
I
FPGA config done
114 D16/TXD6/SDA6/SRXD6/P12_0
USB_SDA
I/O
O
USB I2C data
115 VCC
VCC
---
116
A8/[A8/D8]/TA0OUT/UD0A/UD1A/
P3_0
A[8]
B
O
External b
u
s
117 VSS
VSS
---
118 A7/[A7/D7]/AN2_7/P2_7/TXD10
A[7]
B
O
External b
u
s
119 A6/[A6/D6]/AN2_6/P2_6/RXD10
A[6]
B
O
External b
u
s
120 A5/[A5/D5]/AN2_5/P2_5/CLK10
A[5]
B
O
External b
u
s
121
A4/[A4/D4]/AN2_4/P2_4/N_
CTS10/N_RTS10
A[4]
B
O
External b
u
s
122 A3/[A3/D3]/AN2_3/P2_3/TXD9
A[3]
B
O
External b
u
s
123 A2/[A2/D2]/AN2_2/P2_2/RXD9
A[2]
B
O
External b
u
s
124
A1/[A1/D1]/BC2/[BC2/D1]/AN2_1/
P2_1/CLK9
A[1]
B
O
External b
u
s
125
A0/[A0/D0]/BC0/[BC0/D0]/AN2_0/
P2_0/N_CTS9/N_RTS9
NC
Unconnected (impossible of I/O port
u
se)
126 D15/N_INT5/IIO0_7/IIO1_7/P1_7
D[15]
B
I
External b
u
s
127 D14/N_INT4/IIO0_6/IIO1_6/P1_6
D[14]
B
I
External b
u
s
128 D13/N_INT3/IIO0_5/IIO1_5/P1_5
D[13]
B
I
External b
u
s
67
RX-V471/HTR-4064
RX-V471/HTR-4064
Summary of Contents for HTR-4064
Page 5: ...RX V471 K model RX V471 A model RX V471 B G F models 5 RX V471 HTR 4064 RX V471 HTR 4064 ...
Page 6: ...RX V471 L model RX V471 J model HTR 4064 U model 6 RX V471 HTR 4064 RX V471 HTR 4064 ...
Page 7: ...HTR 4064 G F models HTR 4064 T model HTR 4064 K models 7 RX V471 HTR 4064 RX V471 HTR 4064 ...
Page 124: ... CONFIGURING THE SYSTEM SETTINGS RX V471 HTR 4064 125 ...
Page 125: ... システム設定を変更する RX V471 HTR 4064 126 ...
Page 126: ...127 RX V471 HTR 4064 RX V471 HTR 4064 MEMO ...
Page 127: ...RX V471 HTR 4064 ...
