Yamaha DV-C6280, Service Manual

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DVD-C996/DV-C6280
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ABBREVIATIONS
34 35
E EC ERROR TORQUE CONTROL
ECR ERROR TORQUE CONTROL
REFERENCE
ENCSEL ENCODER SELECT
ETMCLK EXTERNAL M CLOCK (81MHz/40.5MHz)
ETSCLK ETSCLK EXTERNAL S CLOCK (54MHz)
F FBALFCLK FOCUS BALANCE/FRAME CLOCK
FE FOCUS ERROR
FFI FOCUS ERROR AMP INVERTED INPUT
FEO FOCUS ERROR AMP OUTPUT
FG FREQUENCY GENERATOR
FSC FREQUENCY SUB CARRIER
FSCK FS (384 OVER SAMPLING) CLOCK
G GND COMMON GROUNDING (EARTH)
H HA0–UP HOST ADDRESS
HD0–UP HOST DATA
HINT HOST INTERRUPT
HRXW HOST READ/WRITE
I IECOUT IEC958 FORMAT DATA OUTPUT
IPFRAG INTERPOLA TION FLAG
IREF I (CURRENT) REFERENCE
ISEL INTERFACE MODE SELECT
L LDONL LASER DIODE CONTROL
LPC LASER POWER CONTROL
LRCK L CH/R CH DISTINCTION CLOCK
M MA0–UP MEMORY ADDRESS
MCK MEMORY CLOCK
MCKI MEMORY CLOCK INPUT
MCLK MEMORY SERIAL COMMAND CLOCK
MDQ0–UP MEMORY SERIAL COMMAND DATA
MDQM MEMORY DATA INPUT/OUTPUT
MLD MEMORY DATA I/O MASK
MPEG MEMORY SERIAL COMMAND LOAD
MOTION PICTURE IMAGE CODING
EXPERT GROUP
O ODC OPTICAL DISC CONTROLLER
OFTR OFF TRACKING
OSCI OSCILLATOR INPUT
OSCO OSCILLATOR OUTPUT
OSD ON SCREEN DISPLAY
P P1~UP PORT
PCD CD TRACKING PHASE DIFFERENCE
PCK PLL CLOCK
PDVD DVD TRACKING PHASE DIFFERENCE
PEAK CAP. FOR PEAK HOLD
PLLCLKPLLO CHANNEL PLL CLOCK
K
PLL LOCK
PWMCTL PWM OUTPUT CONTROL
PWMDA PULSE WAVE MOTOR DRIVE A
PWMOA, B PULSE WAVE MOTOR OUT A, B
INITIAL/LOGO ABBREVIATIONS
A A0~UP ADDRESS
ACLK AUDIO CLOCK
AD0–UP ADDRESS BUS
ADATA AUDIO PES PACKET DATA
ALE ADDRESS LATCH ENABLE
AMUTE AUDIO MUTE
AREQ AUDIO PES PACKET REQUEST
ARE AUDIO RF
ASI SERVO AMP INVERTED INPUT
ASO SERVO AMP OUTPUT
ASYNC AUDIO WORD DISTINCTION SYNC
B BCK BIT CLOCK (PCM)
BCKIN BIT CLOCK INPUT
BDO BLACK DROP OUT
BLKCK SUB CODE BLOCK CLOCK
BOTTOM CAP. FOR BOTTOM HOLD
BYP BYPATH
BYTCK BYTE CLOCK
C CAV CONSTANT ANGULAR VELOCITY
CBDO CAP. BLACK DROP OUT
CD COMPACT DISC
CDSCK CD SERIAL DATA CLOCK
CDSRDATA CD SERIAL DATA
CDRF CD RF (EFM) SIGNAL
CDV COMPACT DISC-VIDEO
CHNDATA CHANNEL DATA
CKSL SYSTEM CLOCK SELECT
CLV CONSTANT LINEAR VELOCITY
COFTR CAP. OFF TRACK
CPA CPU ADDRESS
CPCS CPU CHIP SELECT
CPDT CPU DATA
CPUADR CPU ADDRESS LATCH
CPUADT CPU ADDRESS DATA BUS
CPUIRQ CPU INTERRUPT REQUEST
CPRD CPU READ ENABLE
CPWR CPU WRITE ENABLE
CS CHIP SELECT
CSYNCIN COMPOSITE SYNC IN
CSYNCOUT COMPOSITE SYNC OUT
D DACCK D/A CONVERTER CLOCK
DEEMP DEEMPHASIS BIT ON/OFF
DEMPH DEEMPHASIS SWITCHING
DIG0~UP FL DIGIT OUTPUT
DIN DATA INPUT
DMSRCK DM SERIAL DATA READ CLOCK
DMUTE DIGITAL MUTE CONTROL
DO DROP OUT
DOUT0–UP DATA OUTPUT
DRF DATA SLICE RF (BIAS)
DRPOUT DROP OUT SIGNAL
DREQ DATA REQUEST
DRESP DATA RESPONSE
DSC DIGITAL SERVO CONTROLLER
DSLF DATA SLICE LOOP FILTER
DVD DIGITAL VIDEO DISC
INITIAL/LOGO ABBREVIATIONS
R RE READ ENABLE
RFENV RF ENVELOPE
RFO RF PHASE DIFFERENCE OUTPUT
RS (CD-ROM) REGISTER SELECT
RSEL PF POLARITY SELECT
RST RESET
RSV RESERVE
S SBI0, 1 SERIAL DATA INPUT
SBO0 SERIAL DATA OUTPUT
SBT0, 1 SERIAL CLOCK
SCK SERIAL DATA CLOCK
SCKR AUDIO SERIAL CLOCK RECEIVER
SCL SERIAL CLOCK
SCLK SERIAL CLOCK
SDA SERIAL DATA
SEG0–UP FL SEGMENT OUTPUT
SELCLK SELECT CLOCK
SEN SERIAL PORT ENABLE
SIN1, 2 SERIAL DATA IN
SOUT1, 2 SERIAL DATA OUT
SPDI SERIAL PORT DATA INPUT
SPDO SERIAL PORT DATA OUTPUT
SPEN SERIAL PORT R/W ENABLE
SPRCLK SERIAL PORT READ CLOCK
SPWCLK SERIAL PORT WRITE CLOCK
SQCK SUB CODE Q CLOCK
SQCX SUB CODE Q DATA READ CLOCK
SRDATA SERIAL DATA
SRMADR SRAM ADDRESS BUS
SRMDT0–7 SRAM DATA BUS 0–7
SS START/STOP
STAT STATUS
STCLK STREAM DATA CLOCK
STD0–UP STREAM DATA
STENABLE STREAM DATA INPUT ENABLE
STSEL STREAM DATA POLARITY SELECT
STVALID STREAM DATA VALIDITY
SUBC SUB CODE SERIAL
SBCK SUB CODE CLOCK
SUBQ SUB CODE Q DATA
SYSCLK SYSTEM CLOCK
T TE TRACKING ERROR
TIBAL BALANCE CONTROL
TID BALANCE OUTPUT 1
TIN BALANCE INPUT
TIP BALANCE INPUT
TIS BALANCE OUTPUT 2
TPSN OP AMP INPUT
TPSO OP AMP OUTPUT
TPSP OP AMP INVERTED INPUT
TRCRS TRACK CROSS SIGNAL
TRON TRACKING ON
TRSON TRAVERSE SERVO ON
INITIAL/LOGO ABBREVIATIONS
V VBLANK V BLANKING
VCC COLLECTOR POWER SUPPLY
VOLTAGE
VCDCONT VIDEO CD CONTROL (TRACKING
BALANCE)
VDD DRAIN POWER SUPPLY VOLTAGE
VFB VIDEO FEED BACK
VREF VOLTAGE REFERENCE
VSS SOURCE POWER SUPPLY VOLTAGE
W WAIT BUS CYCLE WAIT
WDCK WORD CLOCK
WEH WRITE ENABLE HIGH
WSR WORD SELECT RECEIVER
X X X' TAL
XALE X ADDRESS LATCH ENABLE
XAREQ X AUDIO DATA REQUEST
XCDROM X CD ROM CHIP SELECT
XCS X CHIP SELECT
XCSYNC X COMPOSITE SYNC
XDS X DATA STROBE
XHSYNCO X HORIZONTAL SYNC OUTPUT
XHINT XH INTERRUPT REQUEST
XI X' TAL OSCILLATOR INPUT
XINT X INTERRUPT
XMW X MEMORY WRITE ENABLE
XO X' TAL OSCILLATOR OUTPUT
XRE X READ ENABLE
XSRMCE X SRAM CHIP ENABLE
XSRMOE X SRAM OUTPUT ENABLE
XSRMWE X SRAM WRITE ENABLE
XVCS X V-DEC CHIP SELECT
XVDS X V-DEC CONTROL BUS STROBE
XVSYNCO X VERTICAL SYNC OUTPUT
INITIAL/LOGO ABBREVIATIONS