Yamaha DSP-AX763, Service Manual

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RX-V663/HTR-6160/DSP-AX763
RX-V663/HTR-6160/
DSP-AX763
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TXD4
P95
DA1
TB3in
TXD3
P92
RXD3
P90
CLK3
INT8
P145
P144
P143
P142
P141
P140
BYTE
CNVss
P87
P86
RESET
Xout
Vss
Xin
Vcc1
NMI
INT2
INT1
INT0
P81
RXD5
CLK5
TXD5
TA2in
P74
P73
P72
TXDi
XMPWR
LC
iPDET
DTXM
RDYRDS
DRXM
RXDRDS
XMLINK
CLKRDS
RXDR
/ICXM
RSTRDS
XMREV
DIRSDO
/ICADC
/ICDIR
/CSDIR
/ICTI
BYTE
CNVss
/CSTI
/CSDAC
/RESET
Xout
Vss
Xin
Vcc
/NMI
/INTDIR
/INTTI
/HSW_INT
/SPIRDY
RWCK
SDD
SCK
SDM
HDMIMT
MUTETI
CDMODE
HSW_CEC
Asynchronous data output for iPod
Power control output for XM antenna
H: ON, L: OFF (U, C models)
Limiter control output
iPod loaded in DOCK detect
Low when iPod is in Dock
Stop mode (MCU sleep) when set to event counter
Asynchronous data output for XM/DT IC (U, C models)
READY input for RDS IC (G model)
Asynchronous data input for XM/DT IC (U, C models)
Synchronous data input for RDS IC (G model)
LINK ACTIVE input for XM/DT IC (U, C models)
Synchronous clock output for RDS IC (G model)
Setting to Low level standby required
RS-232C reception detect (U, C models)
Used for return trigger from stop mode (MCU sleep) / Connect to 40pin
Reset output for XM/DT IC (U, C models)
Reset output for RDS IC (G model)
ANT_REV input for XM/DT IC
High: Non-compatible antenna
DIR DATA input for CDDA writing
AD converter power down
Initial clear output for DIR
Chip select output for DIR
Initial clear output for TI (DA70Y)
When set to single chip mode: Vss
Processor mode select Low: Single chip mode
High: To Flash included boot mode
To boot mode with hardware resetting of P50=H, P55=L, CNVss=H
Chip select output for TI (DA70Y)
Chip select output for DAC (for both 2ch/8ch)
Reset
Unused, connect to Vcc
Interrupt input for DIR
Interrupt input for TI (DA70Y)
MATSUSHITA CEC microprocessor (13 pins) interrupt input
READY input for TI (DA70Y)
DIR WCK input for CDDA writing
Synchronous data input for DIR, TI (DA70Y), DAC
DIR: 4M, LSBF TI: 1M, MSBF
Synchronous clock output for DIR, TI (DA70Y), DAC
Synchronous data output for DIR, TI (DA70Y), DAC
DIR: 4M, LSBF TI: 1M, MSBF
MDMI AUDIO MUTE input
H: Mute
Mute output (High=MUTE) for TI (DA70Y)
CDDA write mote control output
H: CDDA write mode L: Normal operation mote
MATSUSHITA CEC microprocessor (12 pins) interrupt input
Reset request from MATSUSHITA microprocessor
SO
O
DA
TMR
SO
I
SI
SI
I
SO
IRQ
O
O
I
I
O
O
CS
O
MCU
MCU
CS
CS
MCU
MCU
MCU
MCU
MCU
MCU
IRQ
IRQ
IRQ
I
I
SI
SO
SO
TMR
O
O
I
O
O
DA
O
I
I
I
O
O
O
O
O
O
O
O
O
O
MCU
MCU
O
O
MCU
MCU
MCU
MCU
MCU
I
O
O
IRQ
O
O
O
O
O
TMR
O
O
I
IRQ
I
O
O
I
O
O
O
O
O
O
O
O
O
O
O
O
O
O
MCU
MCU
O
O
MCU
MCU
MCU
MCU
MCU
O
O
O
O
O
O
O
O
O
O
O
O
Function Name
(P.C.B.)
Power ON VPWR OFF STBY Thrh
Port Name
Pin
No.
232C ON [232C OFF] STANDBY [STBY Sleep]
Detail of Function
STBY CEC MCU Sleep [Sleep]
O
O
I
O
[O]
[O]
[O]
O
O
O
O
[O]
[O]
O
(O)
O
O
O
O
MCU
MCU
O
O
MCU
MCU
MCU
MCU
MCU
I
O
O
O
O
[O]
O
O
O
O
O
O
O
I/O