ACU16-C
15
PIN
No.
NAME
I/O
FUNCTION
PIN
No.
NAME
I/O
FUNCTION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
DVSS
DVDD
MCLK
PD
BICK
SDATA
LRCK
SMUTE
CS
DFS
DEM0
CCLK
DEM1
CDTI
DIF0
DIF1
DIF2
-
-
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Digital Ground Pin
Digital Power Supply Pin, 3.3V or 5.0V
Master Clock Input Pin
Power-Down Mode Pin
When at "L",the Ak4393 is in power-down
mode and is held in reset.
The AK4393 should always be reset
upon power-up.
Audio Serial Data Clock Pin
The clock of 64fs or more than is
recommended to be input on this pin.
Audio Serial Data Input Pin
2's complement MSB-first data is input on this pin.
L/R Clock Pin
Soft Mute Pin
When this pin goes "H", soft mute cycle is initiated.
When returning "L",the output mute releases.
Chip Select Pin in serial mode
Doubla speed sampling mode Pin
(Internal pull-down pin)
"L":Normal Speed, "H":Double Speed
De-emphasis Enable pin
Control Data Clock Pin in serial mode
De-emphasis Enable pin
Control Data Input Pin in serial mode
Digital Input Format Pin
15
16
17
18
19
20
21
22
23
24
25
26
27
28
BVSS
VREFL
VREFH
AVDD
AVSS
AOUTR-
AOUTR+
AOUTL-
AOUTL+
VCOM
P/S
CKS0
CKS1
CKS2
I
I
-
-
O
O
O
O
O
O
I
I
I
I
Substrate Ground Pin, 0V
Low Level Voltage Reference Input Pin
High Level Voltage Reference Input Pin
Analog Power Supply Pin,5V
Analog Ground Pin, 0V
Rch Negative analog output Pin
Rch Positive analog output Pin
Lch Negative analog output Pin
Lch Positive analog output Pin
Common Voltage Output Pin,2.6V
Parallel/Serial Select Pin(Internal pull-up pin)
"L":Serial control mode,"H": Parallel control mode
Master Clock Select Pin
AK4393-VF-E2 (XW029A00) DAC
DAC: IC203, 204, 303, 304, 403, 404, 503, 504
PIN
NO.
I/O
FUNCTION
NAME
PIN
NO.
I/O
FUNCTION
NAME
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
DAUX
HDLT
DOUT
VFL
OPT
SYNC
MCC
WC
MCB
MCA
SKSY
XI
XO
P256
LOCK
Vss
TC
DIM1
DIM0
DOM1
DOM0
KM1
I
O
O
O
O
O
O
O
O
O
I
I
O
O
O
O
I
I
I
I
I
Auxiliary input for audio data
Asynchronous buffer operation flag
Audio data output
Parity flag output
Fs x 1 Synchronous output signal for DAC
Fs x 1 Synchronous output signal for DSP
Fs x 64 Bit clock output
Fs x 1 Word clock output
Fs x 128 Bit clock output
Fs x 256 Bit clock output
Clock synchronization control input
Crystal oscillator connection or external
clock input
Crystal oscillator connection
VCO oscillating clock connection
PLL lock flag
Logic section power (GND)
PLL time constant switching output
Data input mode selection
Data input mode selection
Data output mode selection
Data output mode selection
Clock mode switching input 1
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
RSTN
Vdda
CTLN
PCO
(NC)
CTLP
Vssa
TSTN
KM2
KM0
FS1
FS0
CSM
EXTW
DDIN
LR
Vdd
ERR
EMP
CD0
CCK
CLD
I
I
O
I
I
I
I
O
O
I
I
I
O
O
O
O
I
I
System reset input
VCO section power (+5V)
VCO control input N
PLL phase comparison output
VCO control input P
VCO section power (GND)
Test terminal. Open for normal use
Clock mode switching input 2
Clock mode switching input 0
Channel status sampling frequency
display output 1
Channel status sampling frequency
display output 0
Channel status output method selection
External synchronous auxiliary input
word clock
EIAJ (AES/EBU) data input
PLL word clock output
Logic section power (+5 V)
Data error flag output
Channel status emphasis control code
output
3-wire type microcomputer interface data
output
3-wire type microcomputer interface clock
input
3-wire type microcomputer interface load
input
YM3436DK (XG948E0) DIR2 (Digital Format Interface Receiver)
MAIN: IC502
