Yaesu FT-208R, Maintenance Service Manual

Page: 28 / 80

The IF signal is fed to a balanced mixer,
Q214 /Q21s
(2SK193K),
where the 1 6 .9 MHz FM signal is
mixed with a local signal from the VCO, with the
output being at the ultimate transmitting fre­
quency. A three-stage auto-tune resonator between
Q214/Q21s
and
Q216,
along with a filter immediate­
ly following
Q216 (2SC2786L),
provide superior
rejection of spurious signals.
The signal is delivered to a three-stage RF power
amplifier consisting of
Q101 (2SC2512), Q102
(2SC2053) ,
and
Q103 (2SC2196),
resulting in a
power butput of 2.5 watts.
HETERODYNE OSCILLATOR
The heterodyne signal of 1 27 . 1 00- 1 3 1 .09 5 MHz
(Model A,
D,
E), 1 27. 1 00 - 1 29 .0875 MHz
(Model B), 1 27. 1 00-1 3 1 .0875 MHz (Model C)
for the receiver and transmitter is generated by the
PLL circuit just described.
The VCO,
Q201
(2SK192Y) ,
generates a signal
at one of the above frequencies. The oscillator
frequency is controlled by varactor diode
D201 (1 T25) ,
which varies the capacitance of the
oscillator tuned circuit in accordance with a
control voltage. This control voltage is generated
by phase comparator
Q206 ,
as mentioned earlier,
(µPD2819C)
and delivered through a lowpass filter
consisting of
Q2o? (2SK184Y)
and
Q208 (2SC-
2785E),
to the VCO.
This voltage is then fed to varactor diode
D201
,
which changes the output phase of the VCO to
lock with that of the reference signal. The control
voltage is also used to tune the transmitter band­
pass filters and local signal amplifier filter, thus
providing optimum spurious attenuation.
PLL CONTROL SECTION
The PLL Control Unit employs a 4-bit micro­
processor chip,
Q301 (HD44820A07) ,
which
provides various control information for display
control, transmit disable, DTMF encoder, etc. The
reader is referred to the block diagram of the PLL
control Unit for an explanation of the functions
of the CPU. A full description of each logic state
is beyond the scope of this manual.
TECHNICAL NOTES
2-3