Xycom XVME-654, Manual

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Chapter 4 – Programming
4-6
software standpoint, this is desirable because the interrupt vector table, system
parameters, and communication buffers (keyboard) are placed in low DRAM. This
provides more system protection.
Caution
When setting up slave images, the address and other parameters should be set first.
Only after the VMEbus slave image is set up correctly should the VMEbus slave
image be enabled. If a slave image is going to be remapped, disable the slave image
first, and then reset the address. After the image is configured correctly, re-enable the
image.
The VMEbus slave cycle becomes a master cycle on the PCI bus. The PCI-bus arbiter is
the 1489 chip. It arbitrates between the various PCI masters, the CPU, and the Local bus
IDE bus mastering controller. Because the VMEbus cannot be retried, all VMEbus slave
cycles must be allowed to be processed. This becomes a problem when a cycle to a PCI
slave image is in progress while a VMEbus slave cycle to the onboard DRAM is in
progress. The cycle will not give up the PCI bus and the VMEbus slave cycle will not
give up the VMEbus, causing the XVME-654 to become deadlocked. If the XVME-654
is to be used as a master and a slave at the same time, the VMEbus master cycles must
obtain the VMEbus prior to initiating VMEbus cycles.
All VMEbus slave interface cycles are byte-swapped to maintain address coherency.
VMEbus Interrupt Handling
The XVME-654 can service IRQ[7:1]. A register in the Universe chip enables the
interrupt levels that will be serviced by the XVME-654. When a VMEbus IRQ is
asserted, the Universe requests the VMEbus and generates an IACK cycle. Once the
IACK cycle is complete, a PCI-bus interrupt is generated to allow the proper Interrupt
Service Routine (ISR) to be executed. The Universe chip connects to all four PCI-bus
interrupts. These interrupts may be shared by other PCI-bus devices. The BIOS maps the
PCI-bus interrupts to the AT-bus interrupt controllers. AT-bus interrupts must be
uniquely mapped to each device.
Because the PCI devices share interrupt lines, all ISR routines must be prepared to chain
the interrupt vector to allow the other devices to be serviced.
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