Xycom XVME-240, Manual

Page: 40 / 73

XVME-240 Manual
October, 1984
INTERRUPT VECTOR REGISTER (Base A 85H)
7 6 5 4 3 2 1 0
MSB
LSB
Figure 3-8. Interrupt Vector Register
NOTE
The Interrupt Vector Register powers up to an
indeterminate state, and it must be programmed
before interrupts are enabled.
The vector register is programmed by writing the vector address to the module base
a 85H. The vector register is a latch, and a vector address written to it will
not change until a new vector is written in.
The actual vectors and how they are used is dependent upon the system processor.
Please refer to your system processor operating manual for information on interrupt
vectors.
3.3.9 Flag
Outputs Register (Base A 86H)
The DIO provides 8 Flag Output lines which are designed to signal interrupting devices
that their interrupts have been serviced. However, these lines are not physically/elec-
trically dedicated to this application and they may be employed by the user in other
ways (i.e., control or signal lines to external devices, etc.).
The Flag Outputs are controlled via the read/write Flag Outputs
Register.
Each bit in
the Flag Output Register corresponds to one of the Flag Output lines. Figure 3-9
shows a bit map of the Flag Outputs Register.
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