Xycom XVME-240, Manual

Page: 35 / 73

XVME-240 Manual
October, 1984
The
Port
Direction register is cleared to all "0"s (all ports are inputs) by a VME
SYSRESET or by a Soft Reset (see Section 3.3.2 for information on performing a Soft
Reset). Thus when the module is powered-up or when it is reset, the ports will all
automatically be configured as inputs. After power-up or reset it will be necessary to
write to the port direction register to configure any ports for output.
For example, if a DIO module base address is set to lOOOH in the Short I/O Memory,
and if Ports 4 and 7 need to be configured as outputs after power-up, it will be
necessary to write YOH to address 1087H. This write operation will set bits 4 and 7 of
the port direction register to logic "1" and will therefore configure ports 4 and 7 as
output ports.
Changing the direction of a port has no effect on the data stored in the port’s data
latch.
3.3.4 The Interrupt Input
Register
(Base A 8OH)
This 8-bit register provides a convenient location to allow user software/firmware to
determine which externally connected device is sending an interrupt. Each interrupt
input has its own Interrupt Edge Detection circuitry and interrupt latch (refer to
Section 2.4.8 of this manual for information on interrupt edge detection). The
Interrupt Input Register is a "read only" register and it is positioned immediately after
the Interrupt Edge Detection circuitry and latch.
Each bit of the Interrupt Input Register corresponds to one of the 8 interrupt input
lines (refer to Chapter 2 for the physical location of the interrupt input pins in
connectors JKl and JK2). Figure 3-4 shows a bit map of the Interrupt
Input Register.
INTERRUPT INPUT REGISTER (Base A 8OH)
Bit . Bit . .
Bit
Bit Bit Bit Bit
l
Bit
7 6 5 4 3 2 1 0
I
Interrupt Input 3
Interrupt Input 4
Interrupt Input 5
Interrupt Input 0
Interrupt Input 6
Interrupt Input 7
Figure 3-4. Interrupt Input Register
The Interrupt Input Register bits reflect whether or not the individual Interrupt Inputs
have indeed passed interrupt signals through their interrupt edge detection circuits and
latched them
l
lines.
This register does not reflect the current status of the Interrupt Input
3-8