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Xilinx Zynq UltraScale+ ZCU208, User Manual

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Page: 7 / 35

Xilinx Zynq UltraScale+ ZCU208 User Manual Download Page 7

• Protocol used to communicate between the host computer (GUI) and the software design (see

Chapter 5: Protocol Specifications

Installation

See the

RF DC Evaluation Tool for ZCU208 Board Quick Start

RF DC Evaluation Tool for

ZCU216 Board Quick Start

website for installation and folder structure information.

Chapter 2: Overview

UG1433 (v1.2) October 27, 2021

RF Data Converter Evaluation Tool User Guide

7

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Summary of Contents for Zynq UltraScale+ ZCU208

Page 1: ...e removing non inclusive language from our products and related collateral We ve launched an internal initiative to remove language that could exclude people or reinforce historical biases including t...

Page 2: ...User Space Components Added note to refer to appendix Software Build Revised the steps for making the SD card images and copying files to the SD card Appendix A Software Design Notes Multimaster Acces...

Page 3: ...Space Components 19 Kernel Space Components 20 Software Build 21 Chapter 5 Protocol Specifications 23 Protocol Overview 23 Protocol Rules 24 Socket Interface 25 Appendix A Software Design Notes Multi...

Page 4: ...References 34 Please Read Important Legal Notices 35 UG1433 v1 2 October 27 2021 www xilinx com RF Data Converter Evaluation Tool User Guide 4 Send Feedback...

Page 5: ...The evaluation tool can be used to jump start RF class analog designs and to demonstrate the capabilities and excellent performance of the Gen 3 RF data converters Advantages of using this tool inclu...

Page 6: ...igure shows the evaluation tool and test platform overview Figure 1 Evaluation Tool and Test Platform Overview X24062 062220 The tool is built from these components ZCU208 Evaluation Board User Guide...

Page 7: ...tions Installation See the RF DC Evaluation Tool for ZCU208 Board Quick Start or the RF DC Evaluation Tool for ZCU216 Board Quick Start website for installation and folder structure information Chapte...

Page 8: ...A53 PL DDR4 support including DMA AXI4 Stream broadcaster and switch and GPIO control Clocking scheme to support DDR4 and multi tile synchronization I2C connection to control external clocks CLK104 s...

Page 9: ..._AXIS S11_AXIS S12_AXIS S13_AXIS S20_AXIS S21_AXIS S22_AXIS S23_AXIS S30_AXIS S31_AXIS S32_AXIS S33_AXIS S00_AXIS S01_AXIS S02_AXIS S03_AXIS DAC_DMA_DDR RF_Analyzer ADC_DDR_DMA Dout 0 0 Dout1 0 0 Dout...

Page 10: ...XIS0 M_AXIS1 M_AXIS2 M_AXIS3 M_AXIS4 M_AXIS5 M_AXIS6 M_AXIS7 M_AXIS8 M_AXIS9 M_AXIS10 M_AXIS11 M_AXIS12 M_AXIS13 M_AXIS14 M_AXIS15 S_AXIS S_AXIS1 S_AXIS2 S_AXIS3 M_AXIS M_AXIS1 M_AXIS2 M_AXIS3 Clock_C...

Page 11: ...S_AXIS12 S_AXIS13 S_AXIS14 S_AXIS15 S_AXI_CTRL s_axis s00_AXI m_axis tlast_gen_v1_0_0 S_AXI_LITE S_AXIS_S2MM M_AXI_SG M_AXI_S2MM axi_dma_0 tlast_gen_v1_0 Pre Production AXI Direct Memory Access Pre P...

Page 12: ...ocked loop PLL which gives an independent clock per tile The second clocking scheme supports MTS takes its input from a fabric pin and generates an output for the tiles selected by the MTS functions B...

Page 13: ...2 RF DAC Tile 0 X23667 052820 TDD Control Block The TDD control hardware block demonstrates the TDD power up down of each ADC and DAC channel The block can be used as a reference on how to drive the...

Page 14: ...ion Figure 8 Frames and Symbols Representation Guard Band Guard Band DL UL DL UL Guard Band Guard Band DL UL DL UL Frame 9 of N Symbols Frame 10 of N Symbols Frame 1 of N Symbols Frame 2 of N Symbols...

Page 15: ...bit n DAC channel n 0x4 ADC TDD mode pin bit n ADC channel n 0x8 Bit 0 reset others reserved 0xC Bit 0 to 3 ADC hw_trigger_en control 0x10 Symbol to trigger on 0x14 Frame to trigger on 0x18 Arm the t...

Page 16: ...rame 2 of N Symbols Frame 3 of N Symbols Frame 4 of N Symbols Frame 5 of N Symbols UL UL UL UL Frame 6 of N Symbols UL Frame 7 of N Symbols Frame 8 of N Symbols Frame 9 of N Symbols Frame 10 of N Symb...

Page 17: ...rols the hw_trigger_en pins In this example it enables the trigger on tile 1 Write 1 in the trigger register SetTDDRTSTrig 1 This controls the hw_trigger pins Chapter 3 Hardware Design UG1433 v1 2 Oct...

Page 18: ...to control hardware All configurations of the RF ADCs and RF DACs are done by the Linux application rftool running on the processing system PS The application supports all the configuration options s...

Page 19: ...Engine TCP IP stack AXI DMA Driver GEM driver lic driver UIO Hardware GEM I2C CLK104 GPIO Controller Memory RFDC IP AXI Infrastructure AXI DMAs MMCM Libmetal X23668 031920 User Space Components The L...

Page 20: ...over the TCP socket The stack uses the GEM driver to send and receive packets from a network interface card NIC The DMA client driver provides the interface for a user application to trigger DMA tran...

Page 21: ...e 2019 2 version of the PetaLinux Tools Documentation PetaLinux Command Line Reference UG1157 1 Ensure the PetaLinux tools are available in the PATH environment variable 2 To create the project enter...

Page 22: ...s linux u boot elf 5 Copy these files to the SD card project_name images linux BOOT BIN project_name images linux image ub project_name images linux boot scr autostart sh copy from the Externals image...

Page 23: ...in text ASCII format parsed to check that the command is known and the number of arguments is correct and then executed The design returns the command name plus some parameters or the error type witho...

Page 24: ...s n The output return format is If an input command is not recognized the parser errors out and sends ERROR CMD Invalid Command n If an input command is recognized the parser checks the number of argu...

Page 25: ...SoC PS The control path works on TCP port 8081 and the datapath works on TCP port 8082 The TCP socket uses a Linux TCP IP stack which uses the GEM Ethernet controller and driver for sending packets Be...

Page 26: ...on to select the CLK104 device on the multiplexer and read write operation is completed in three steps in the I2C driver When one master is accessing the device the other master should not access it A...

Page 27: ...uation tool GUI GetLog None Logged Strings Uses metal_log to return any error warning or informational messages returned from the API or command interface JtagIdcode None Idcode Return the device JTAG...

Page 28: ...Block Settings CoarseDelay Settings EventSource Cf PG269 GetConnectedData Type Tile Block Type Tile Block ConnectedIData ConnectedQData Cf PG269 GetDACCompMode Tile Block Tile Block EnablePtr Cf PG26...

Page 29: ...eresisEnable Cf PG269 GetDACPower Board_id Tile Board_id Tile value_1 value_2 value_3 value_4 value_5 Cf PG269 IntrClr Type Tile Block IntrMask None Cf PG269 IntrDisable Type Tile Block IntrMask None...

Page 30: ...Distribution_Settings Info ClkSettings Type Tile_Id SampleRate Distribution_Settings Info ClkSettings Type Tile_Id DivisionFactor Distribution_Settings Info ClkSettings Type Tile_Id DistributedClock D...

Page 31: ...eff0 Coeffs Coeff1 Coeffs Coeff2 Coeffs Coeff3 Coeffs Coeff4 Coeffs Coeff5 Coeffs Coeff6 Coeffs Coeff7 Cf PG269 DisableCoefficientsOverride Tile Block CalBlock None Cf PG269 SetDACCompMode Tile Block...

Page 32: ...v Get the MMCM settings MMCM_Rst Type Tile None Reset the MMCM LocalMemInfo Type Type memBaseAddr numTiles numMem memSize numWords mem_enable mem_clksel Get information on the memory LocalMemTrigger T...

Page 33: ...igger 0 stop triggering the memory automatically via hw_trigger 1 enable triggering of capture memories SetTDDRTSTrigSlot Trig_symbol trig_frame None Set the frame and symbol to trigger on GetTDDRTSTr...

Page 34: ...sign Tools DocNav At the Linux command prompt enter docnav Xilinx Design Hubs provide links to documentation organized by design tasks and other topics which you can use to learn key concepts and addr...

Page 35: ...loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same Xilinx assumes no obligation to correct any errors contained in the Materials or to notify you of updates to t...

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