Xilinx Zynq UltraScale+ ZCU208, User Manual

Page: 33 / 35

Table 3: Command List (cont'd)
Command Input Parameters Output Parameters Description
GetTDDRTSTrigDelay Tile Trig_Delay
Get the trigger delay
for ADC per tile. This
is the delay between
the TDD trigger (from
SetTDDRTSTrigSlot) to
the hw_trigger of the
capture memory.
Delay in AXI control
clock cycles (slow
clock), then resync to
tile clock.
SetTDDRTSTrigDelay Tile, Trig_Delay None
Set the trigger delay
for ADC per tile. This
is the delay between
the TDD trigger (from
SetTDDRTSTrigSlot) to
the hw_trigger of the
capture memory.
Delay in AXI control
clock cycles (slow
clock), then resync to
tile clock.
SetTDDRTSTrig Trig None
Set the trigger. 0: stop
triggering the
memory
automatically via
hw_trigger. 1: enable
triggering of capture
memories.
GetTDDRTSTrig None Trig
Get the trigger. 0:
stop triggering the
memory
automatically via
hw_trigger. 1: enable
triggering of capture
memories.
SetTDDRTSTrigSlot Trig_symbol, trig_frame None
Set the frame and
symbol to trigger on.
GetTDDRTSTrigSlot None Trig_symbol, trig_frame
Get the frame and
symbol to trigger on.
GetTDDRTSSlot None Guard_Length, Symbol_Length, Slot_Config
Get configuration of
guard band, symbol
length, and slot
configuration (UL/DL).
SetTDDRTSSlot
Guard_Length, Symbol_Length,
Slot_Config
None
Set configuration of
guard band, symbol
length, and slot
configuration (UL/DL).
GetTDDRTSEnables None Enables
Read the enable/
disable hw_trigger_en
on capture mem, per
tile.
SetTDDRTSEnables Enables None
Set the enable/disable
hw_trigger_en on
capture mem, per tile.
SetTDDRTSRst Reset None
Reset the counters in
the TDD block.
SetTDDRTSRst None Reset
Read the reset
register.
Appendix B: Command List
UG1433 (v1.2) October 27, 2021 www.xilinx.com
RF Data Converter Evaluation Tool User Guide 33
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