XtremeDSP Spartan-3A DSP Development Board - Technical reference guide - v1.1
30
DDR2 memory
DDR2 memory expansion
The SODIMM connector allows you to install DDR2 SODIMM modules with more memory because higher
order addresses and chip select signals are also routed from the SODIMM connector to the FPGA. However, a
permanent limitation is that only the first 32 bits of data are routed to the FPGA.
DDR2 clock signal
Two, matched length pairs of DDR2 clock signals are broadcast from the FPGA to the SODIMM connector. The
FPGA design is responsible for driving the two clock pairs at a low skew. The delay on the clock traces is
designed to match the delay of the other DDR2 control signals.
DDR2 signaling
All DDR2 control signals are terminated through 47-
Ω
resistors to a 0.9-V VTT reference voltage. The DDR2
interface of the FPGA supports SSTL18 signaling and all the DDR2 signals are controlled impedances. The
DDR2 data, mask, and strobe signals are of matched length within byte groups. On die termination (ODT) is
available and better performance can be achieved when used by the memory controller.
MIG compatibility
Since MIG doesn’t directly generate compatible design for the XtremeDSP Spartan-3A DSP Development Board
at this time, the used design can’t be called MIG-compatible. However, the board can be used with a modified
design from MIG.
I
2
C bus addressing
The XtremeDSP Spartan-3A DSP Development Board uses an I
2
C bus to interface different devices to the
FPGA. The following table shows the slave addresses of these devices:
Table 21 I
2
C slave device addresses
Device
A7
A6
A5
A4
A3
A2
A1
A0
Fan
controller
0 1 0 1 1 0 0
R/W
Video
encoder
1 1 1 0 1 1 0
R/W
Digital potentiometer for
FMC power supply
adjustment
0 1 0 1 0 0 0
R/W
I
2
C
EEPROM
1 0 1 0 1 0 0
R/W
Clock
generator
1 1 0 1 0 1 0
R/W
FMC module I
2
C
EEPROM
1 0 1 0 X 0 0
R/W
Note
The FMC module’s manufacturer supplies the value of A3.
