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Xilinx Spartan-3A DSP FPGA Series, Technical Reference Manual

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Xilinx Spartan-3A DSP FPGA Series Technical Reference Manual Download Page 11

Hardware overview 

   11 

Hardware overview 

This chapter presents an overview the XtremeDSP Spartan-3A DSP Development Board by describing its parts 
and functions. 

XtremeDSP Spartan-3A DSP Development Board block diagram 

The XtremeDSP Spartan-3A DSP Development Board can be represented by the following block diagram: 

 

Figure 1  XtremeDSP Spartan-3A DSP Development Board block diagram 

Summary of Contents for Spartan-3A DSP FPGA Series

Page 1: ...e eD DS SP P S Sp pa ar rt ta an n 3 3A A D DS SP P D De ev ve el lo op pm me en nt t B Bo oa ar rd d T Te ec ch hn ni ic ca al l R Re ef fe er re en nc ce e G Gu ui id de e S Se ep pt te em mb be er...

Page 2: ...part of this document may be reproduced or used in any form or by any means graphical electronic or mechanical which includes photocopying recording taping and information storage retrieval systems w...

Page 3: ...C62x C64x and C67x are trademarks of Texas Instruments Incorporated All other product names are trademarks or registered trademarks of their respective holders The TM and marks have been omitted from...

Page 4: ...4 This page was left intentionally blank...

Page 5: ...ications outlines the major specifications of the XtremeDSP Spartan 3A DSP Development Board Conventions In a procedure containing several steps the operations that the user has to execute are numbere...

Page 6: ...ted to providing the highest level of customer service and product support If you experience any difficulties when using the XtremeDSP Spartan 3A DSP Development Board or if it fails to operate as des...

Page 7: ...ansion connector 29 DDR2 memory 30 DDR2 memory expansion 30 DDR2 clock signal 30 DDR2 signaling 30 MIG compatibility 30 I2 C bus addressing 30 Configuration options 31 JTAG configuration 31 Board flas...

Page 8: ...XtremeDSP Spartan 3A DSP Development Board Technical reference guide v1 1 8 This page was left intentionally blank...

Page 9: ...ration 14 Table 3 Soft Touch connector pin assignments 15 Table 4 FMC expansion connector pin assignments 1 16 Table 5 FMC expansion connector pin assignments 2 17 Table 6 Mictor pin assignments 18 Ta...

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Page 11: ...artan 3A DSP Development Board by describing its parts and functions XtremeDSP Spartan 3A DSP Development Board block diagram The XtremeDSP Spartan 3A DSP Development Board can be represented by the f...

Page 12: ...nd peripheral modes of operation see 2 and 3 The USB controller also has two serial interface engines SIE that can be used independently SIE1 is connected to the USB host port 3 SIE2 is connected to t...

Page 13: ...DSP Development Board 4 AC 97 SoundaMAX codec Analog Devices AD1981B The device supports 16 bit stereo audio and sampling rates up to 48 kHz The sampling rate for recording and playback may also be di...

Page 14: ...thernet port 10Base T 100Base TX and 1000Base T Gigabit Ethernet port Connected to the Ethernet PHY 8 10 Flash memory Intel StrataFlash embedded memory JS28F256P30B95 Provides the development board wi...

Page 15: ...GND A18 M9 FMC_LA12_N B18 L7 FMC_LA13_N A19 T5 FMC_LA33_P B19 V1 FMC_LA11_P A20 NC GND B20 NC GND A21 U4 FMC_LA33_N B21 V2 FMC_LA11_N A22 P7 FMC_LA24_P B22 R5 FMC_LA25_P A23 NC GND B23 NC GND A24 P6 F...

Page 16: ...29N D11 D3 LA00P C12 NC GND D12 E4 LA00N C13 NC GND D13 NC GND C14 K5 LA30P D14 E3 LA01P C15 K4 LA30N D15 F4 LA01N C16 NC GND D16 NC GND C17 NC GND D17 K7 LA02P C18 J5 LA31P D18 J6 LA02N C19 J4 LA31N...

Page 17: ...G7 L9 LA17N H7 F5 LA06P G8 NC GND H8 G4 LA06N G9 H2 LA18P H9 NC GND G10 H1 LA18N H10 B2 LA07P G11 NC GND H11 B1 LA07N G12 M8 LA19P H12 NC GND G13 M7 LA19N H13 E1 LA08P G14 NC GND H14 F2 LA08N G15 J7...

Page 18: ...for 3 3 V to use the memory See FMC expansion connector for instructions about how to properly configure the adjustable power supply The ZBT synchronous SRAM shares the same data bus as the flash mem...

Page 19: ...r When no FMC expansion module is present the output voltage of PS1 should be set to 3 3 V with the I2 C bus interface to configure the digital potentiometer U28 See I2 C bus addressing for details Th...

Page 20: ...33 MHz System ACE clock 4_N 33 MHz FPGA clock FPGA pin AE13 5_P 200 MHz FPGA differential clock P FPGA pin AA13 5_N 200 MHz FPGA differential clock N FPGA pin Y13 6 27 MHz FPGA clock FPGA pin AF13 22...

Page 21: ...line resolution LCD to display text information The data interface to the LCD is connected to the FPGA and supports only the 4 bit mode Onboard level shifters are used to shift the voltage level betw...

Page 22: ...0 configuration jumpers are present on the XtremeDSP Spartan 3A DSP Development Board The following tables describes how to use them Table 13 Configuration jumpers Jumper Function On Off JP1 Prevents...

Page 23: ...tion 1 DS10 W23 GPIO_LED_0 2 DS11 V22 GPIO_LED_1 3 DS12 V25 GPIO_LED_2 4 DS13 V24 GPIO_LED_3 5 DS14 V23 GPIO_LED_4 6 DS15 U23 GPIO_LED_5 7 DS16 U22 GPIO_LED_6 8 DS17 T24 GPIO_LED_7 33 Configuration DI...

Page 24: ...I EEPROM 0 0 1 MASTER BPI UP NOT SUPPORTED 0 1 0 MASTER BPI DOWN NOT SUPPORTED 0 1 1 MASTER SELECTMAP CONFIG FROM XCF32P FLASH 1 0 0 JTAG CONFIG FROM SYSTEMACE 1 0 1 SLAVE SELECTMAP CONFIG FROM XCF32P...

Page 25: ...onnectors Microphone line in line out and headphones connectors All the connectors are stereo except the microphone connector Table 19 Audio connectors Connector Function J8 Microphone In J9 Analog li...

Page 26: ...e rank unregistered 512 MB DDR2 SDRAM The DDR2 SDRAM is ususlly a Micron MT8HTF6464HY 53E or similar Serial presence detection SPD through an I2 C interface to the memory is also supported by the FPGA...

Page 27: ...23 DDR2_0_BA_1 M21 DDR2_0_DQ_15 AC26 DDR2_0_BA_2 G24 DDR2_0_DQ_16 U20 DDR2_0_CAS_B G23 DDR2_0_DQ_17 U18 DDR2_0_CK0_N K22 DDR2_0_DQ_18 U19 DDR2_0_CK0_P M19 DDR2_0_DQ_19 D26 DDR2_0_CK1_N F24 DDR2_0_DQ_2...

Page 28: ...s used for the USB interface are shared with the System ACE interface See the FPGA pinout on Table 1 Note Configuration with the System ACE controller is enabled with the configuration DIP switches Th...

Page 29: ...nine I2 C EEPROM is not defined at this time A work group is currently developing the Vita 57 2 standard The standard should be released soon To set the appropriate voltage on the FMC connector an I2...

Page 30: ...g and all the DDR2 signals are controlled impedances The DDR2 data mask and strobe signals are of matched length within byte groups On die termination ODT is available and better performance can be ac...

Page 31: ...ted for appropriate JTAG operation The JTAG chain can be used to program the FPGA and access the FPGA for hardware and software troubelshooting The JTAG header s connection to the JTAG chain allows a...

Page 32: ...board flash memory can download bitstreams under master serial slave serial master SelectMAP parallel or slave SelectMAP parallel modes Using iMPACT to program the memory you can select which of the f...

Page 33: ...ndensing Storage temperature range 55 C to 150 C non condensing Maximum power consumption 6 84 W Notes These power consumption specifications were calculated with a production test bitstream The power...

Page 34: ...2 serial port System ACE Compact Flash JTAG programming interface Video DVI VGA output Audio in 2 line and microphone Audio out 2 line and amplifier USB 2 host and peripheral LCD 2 16 CompactFlash con...

Page 35: ...les and recommendations violated on the XtremeDSP Spartan 3A DSP Development Board Table 22 FMC standard rule and recommendation violations Rule Recommendation Violation Rule 27 No available front pan...

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Page 37: ...IDT Web site at this address www1 idt com genID 5V9885 2 To download the ZIP file of the program in the Related Documents group at the bottom of the page click Programming Software 3 Unzip and instal...

Page 38: ...nder Output Clock Frequencies type the clock output frequencies in the appropriate text boxes 7 To calculate the register values necessary to produce the clock frequencies click Auto Calculate The Aut...

Page 39: ...the settings from register 0xC to register 0xF and so on Figure 8 presents how the contents are copied for registers 0x13 0x17 0x1B and 0x21 Table 23 Register configuration Register address Config 0 R...

Page 40: ...t Boundary Scan 5 Right click the device and click Assign New Configuration File on the shortcut menu that appears 6 Locate the SVF file sdsp_clock_setup svf as the example below and then click Open 7...

Page 41: ...Appendix 1 Clock generator programming 41 This page was left intentionally blank...

Page 42: ......

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