SP601 Hardware User Guide
www.xilinx.com
19
UG518 (v1.1) August 19, 2009
Detailed Description
X-Ref Target - Figure 1-7
Figure 1-7:
SPI Flash Interface Topology
Table 1-6:
SPI x4 Memory Connections
FPGA U1
Pin
Schematic Netname
SPI MEM U17
SPI HDR J12
Pin #
Pin Name
Pin #
Pin Name
V2
FPGA_PROG_B
1
V14
FPGA_D2_MISO3
1
IO3_HOLD_B
2
T14
FPGA_D1_MISO2_R
9
IO2_WP_B
3
V3
SPI_CS_B
4
TMS
T13
FPGA_MOSI_CSI_B_MISO0
15
DIN
5
TDI
R13
FPGA_D0_DIN_MISO_MISO1
8
IO1_DOUT
6
TDO
R15
FPGA_CCLK
16
CLK
7
TCK
8
GND
9
VCC3V3
J15.2
SPIX4_CS_B
7
CS_B
U1
FPGA
S
PI INTERFACE
U17
J12
S
PI X4
FLA
S
H
MEMORY
WINBOND
W25Q64V
S
FIG
S
PI PROGRAM
HEADER
S
PI
S
ELECT
JUMPER
ON =
S
PI X4 U17
OFF =
S
PI EXT. J12
S
PIX4_C
S
_B
DIN,DOUT,CCLK
S
PI_C
S
_B
2
J15
1
UG51
8
_07_070
8
09