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SP601 Hardware User Guide

www.xilinx.com

UG518 (v1.1) August 19, 2009

Appendix B

Default Jumper and Switch Settings

Table B-1

shows the default jumper and switch settings for the SP601.

Table B-1:

Default Jumper and Switch Settings

REFDES

Type/Function Default

SW1

SLIDE, POWER ON-OFF

OFF

SW2

DIP, 2-POLE, MODE

ON (1)

OFF (0)

SW8

DIP, 4-POLE, GPIO

OFF

HDR_1X3, JTAG BYPASS

JUMP 1-2 (EXCLUDE FMC)

J14

HDR_1X2, SUSPEND

OPEN (0 = AWAKE)

J15

HDR_1X2, SPI SELECT

ON (U17 SPI MEM SELECTED)

Summary of Contents for SP601

Page 1: ...Guide Subtitle optional UG518 v1 1 August 19 2009 optional SP601 Hardware User Guide UG518 v1 1 August 19 2009...

Page 2: ...s contained in the Documentation or to advise you of any corrections or updates Xilinx expressly disclaims any liability in connection with technical support or assistance that may be provided to you...

Page 3: ...this document Date Version Revision 07 15 2009 1 0 Initial Xilinx release 08 19 2009 1 1 Added Appendix C VITA 57 1 FMC Connections Updated Figure 1 18 and Figure 1 32 Updated Table 1 4 Table 1 17 an...

Page 4: ...SP601 Hardware User Guide www xilinx com UG518 v1 1 August 19 2009...

Page 5: ...DDR2 Component Memory 14 3 SPI x4 Flash 18 4 Linear Flash BPI 20 5 10 100 1000 Tri Speed Ethernet PHY 23 6 USB to UART Bridge 25 7 IIC Bus 26 8 Kb NV Memory 27 8 Clock Generation 27 Oscillator Differ...

Page 6: ...www xilinx com SP601 Hardware User Guide UG518 v1 1 August 19 2009 Appendix A References Appendix B Default Jumper and Switch Settings Appendix C VITA 57 1 FMC Connections Appendix D SP601 Master UCF...

Page 7: ...Appendix D SP601 Master UCF Additional Resources To search the database of silicon and software questions and answers or to create a technical support case in WebCase see the Xilinx website at http w...

Page 8: ...which you must choose one or more lowpwr on off Vertical bar Separates items in a list of choices lowpwr on off Angle brackets User defined variable or in code samples directory name Vertical ellipsis...

Page 9: ...tion Additional information and support material is located at http www xilinx com sp601 This information includes Current version of this user guide in PDF format Example design files for demonstrati...

Page 10: ...nal access 2 pin header VITA 57 1 FMC LPC connector 8 Clock Generation Oscillator Differential Oscillator Socket Single Ended 2 5V or 3 3V SMA Connectors Differential 9 VITA 57 1 FMC LPC Connector 10...

Page 11: ...mentation on Xilinx tools and solutions ISE www xilinx com ise Answer Browser www xilinx com support Intellectual Property www xilinx com ipcenter X Ref Target Figure 1 1 Figure 1 1 SP601 Features and...

Page 12: ...hoto 1 1 7 7 2 2 3 3 4 4 5 5 6 6 8 8 9 9 10 10 12 12 13 13 14 14 15 15 8 8 16 16 11 11 13 13 Table 1 1 SP601 Features Number Feature Notes Schematic Page 1 Spartan 6 FPGA XC6SLX16 2CSG324 2 DDR2 Compo...

Page 13: ...8V DDR2 component memory interface of Spartan 6 FPGA s hard memory controller The voltage applied to the FPGA I O banks used by the SP601 board is summarized in Table 1 2 9 VITA 57 1 FMC LPC connector...

Page 14: ...rity is maintained through DDR2 resistor terminations and memory on die terminations ODT as shown in Table 1 3 and Table 1 4 2 2 5V 3 1 8V Table 1 2 I O Voltage Rail of FPGA Banks Cont d FPGA Bank I O...

Page 15: ...R2_A2 M7 A2 L7 DDR2_A3 N2 A3 F3 DDR2_A4 N8 A4 H4 DDR2_A5 N3 A5 H3 DDR2_A6 N7 A6 H6 DDR2_A7 P2 A7 D2 DDR2_A8 P8 A8 D1 DDR2_A9 P3 A9 F4 DDR2_A10 M2 A10 D3 DDR2_A11 P7 A11 G6 DDR2_A12 R2 A12 L2 DDR2_DQ0...

Page 16: ...F3 LDM K4 DDR2_UDM B3 UDM X Ref Target Figure 1 3 NET DDR2_A12 LOC G6 IOSTANDARD SSTL18_II NET DDR2_A11 LOC D3 IOSTANDARD SSTL18_II NET DDR2_A10 LOC F4 IOSTANDARD SSTL18_II NET DDR2_A9 LOC D1 IOSTAND...

Page 17: ...STL18_II NET DDR2_DQ7 LOC J1 IOSTANDARD SSTL18_II NET DDR2_DQ6 LOC J3 IOSTANDARD SSTL18_II NET DDR2_DQ5 LOC H1 IOSTANDARD SSTL18_II NET DDR2_DQ4 LOC H2 IOSTANDARD SSTL18_II NET DDR2_DQ3 LOC K1 IOSTAND...

Page 18: ...ng an external SPI flash memory device The SP601 SPI interface has two parallel connected configuration options see Figure 1 7 an SPI X4 Winbond W25Q64VSFIG 64 Mb flash memory device and a flash progr...

Page 19: ...Pin Pin Name V2 FPGA_PROG_B 1 V14 FPGA_D2_MISO3 1 IO3_HOLD_B 2 T14 FPGA_D1_MISO2_R 9 IO2_WP_B 3 V3 SPI_CS_B 4 TMS T13 FPGA_MOSI_CSI_B_MISO0 15 DIN 5 TDI R13 FPGA_D0_DIN_MISO_MISO1 8 IO1_DOUT 6 TDO R15...

Page 20: ...3D devices operate at 3 0V the Spartan 6 FPGA I Os are 3 3V tolerant and provide electrically compatible logic levels to directly access the linear flash BPI through a 2 5V bank For details on configu...

Page 21: ...SH_A16 8 A16 H12 FLASH_A17 7 A17 D18 FLASH_A18 6 A18 D17 FLASH_A19 5 A19 G14 FLASH_A20 4 A20 F14 FLASH_A21 3 A21 C18 FLASH_A22 1 A22 C17 FLASH_A23 30 A23 F16 FLASH_A24 56 A24 R13 FPGA_D0_DIN_MISO_MISO...

Page 22: ...4 LOC G18 NET FLASH_A5 LOC G16 NET FLASH_A6 LOC H16 NET FLASH_A7 LOC H15 NET FLASH_A8 LOC H14 NET FLASH_A9 LOC H13 NET FLASH_A10 LOC F18 NET FLASH_A11 LOC F17 NET FLASH_A12 LOC K13 NET FLASH_A13 LOC K...

Page 23: ...ed over the MDIO interface Table 1 8 PHY Configuration Pins Pin Connection on Board Bit 2 Definition and Value Bit 1 Definition and Value Bit 0 Definition and Value CFG0 VCC 2 5V PHYADR 2 1 PHYADR 1 1...

Page 24: ...T PHY_RESET LOC L13 NET PHY_RXCLK LOC L16 NET PHY_RXCTL_RXDV LOC N18 NET PHY_RXD0 LOC M14 NET PHY_RXD1 LOC U18 NET PHY_RXD2 LOC U17 NET PHY_RXD3 LOC T18 NET PHY_RXD4 LOC T17 NET PHY_RXD5 LOC N16 NET P...

Page 25: ...receive RX Request to Send RTS and Clear to Send CTS Silicon Labs provides royalty free Virtual COM Port VCP drivers which permit the CP2103GM USB to UART bridge to appear as a COM port to host comput...

Page 26: ...e SP601 IIC bus topology is shown in Figure 1 13 The IIC Bus on the SP601 provides access to a 2 pin header the onboard 8 Kb EEPROM and the VITA 57 1 FMC interface The user must ensure there are no II...

Page 27: ...cillator Differential The SP601 has one 2 5V LVDS differential 200 MHz oscillator U5 soldered onto the board and wired to an FPGA global clock input Crystal oscillator Epson EG2121CA PPM frequency jit...

Page 28: ...The Samtec connector system is rated for signaling speeds up to 9 GHz 18 Gb s based on a 3dB insertion loss point within a two level signaling environment Refer to the Samtec website for data sheets...

Page 29: ...LA07_P LA08_N NC NC GND GND NC NC 14 NC NC LA07_N GND NC NC LA09_P LA10_P NC NC 15 NC NC GND LA12_P NC NC LA09_N LA10_N NC NC 16 NC NC LA11_P LA12_N NC NC GND GND NC NC 17 NC NC LA11_N GND NC NC LA13...

Page 30: ...1_N NC NC TRST_L GA0 NC NC 35 NC NC LA30_N GND NC NC GA1 12P0V NC NC 36 NC NC GND LA33_P NC NC 3P3V GND NC NC 37 NC NC LA32_P LA33_N NC NC GND 12P0V NC NC 38 NC NC LA32_N GND NC NC 3P3V GND NC NC 39 N...

Page 31: ...LA13_P LOC B11 NET FMC_LA14_N LOC A2 NET FMC_LA14_P LOC B2 NET FMC_LA15_N LOC F9 NET FMC_LA15_P LOC G9 NET FMC_LA16_N LOC A7 NET FMC_LA16_P LOC C7 NET FMC_LA17_CC_N LOC T8 NET FMC_LA17_CC_P LOC R8 NET...

Page 32: ...100 DS4 PHY_LED_LINK100 0 Green 1000 DS5 PHY_LED_DUPLEX Green DUP DS6 PHY_LED_RX Green RX DS7 PHY_LED_TX Green TX DS8 FPGA_AWAKE Green AWAKE DS9 FPGA_DONE Green DONE Illuminates to indicate the statu...

Page 33: ...on user_guides ug380 pdf X Ref Target Figure 1 19 Figure 1 19 FPGA Awake LED and Suspend Jumper FPGA AWAKE R88 27 4 1 1 16W 1 2 LED GRN SMT 2 DS8 1 R18 4 7K 5 1 16W 1 2 J14 Suspend Jumper OFF AWAKE de...

Page 34: ...loaded and the FPGA successfully configured X Ref Target Figure 1 21 Figure 1 21 FPGA INIT and DONE LEDs INIT_B 0 LED ON INIT_B 1 LED OFF FPGA INIT B FPGA DONE VCC2V5 VCC2V5 VCC2V5 R23 4 7K 5 1 16W R9...

Page 35: ...partial UCF in Figure 1 27 User LEDs The SP601 provides four active high green LEDs as described in Figure 1 23 and Table 1 17 X Ref Target Figure 1 23 Figure 1 23 User LEDs Table 1 17 User LEDs Refer...

Page 36: ...ser LEDs Cont d Reference Designator Signal Name Color Label FPGA Pin X Ref Target Figure 1 24 Figure 1 24 User DIP Switch UG518_24_070809 R22 4 7K 5 1 16W R21 4 7K 5 1 16W R20 4 7K 5 1 16W R19 4 7K 5...

Page 37: ...pushbuttons are assigned as GPIO and the fifth is assigned as a CPU_RESET Figure 1 25 and Table 1 19 describe the pushbutton switches X Ref Target Figure 1 25 Figure 1 25 User Pushbutton Switch Typica...

Page 38: ...GPIO Male Pin Header Topology 1 2 3 4 5 6 7 8 9 10 11 12 J13 VCC3V3 GPIO HDR4 GPIO HDR0 GPIO HDR1 GPIO HDR2 GPIO HDR3 GPIO HDR5 GPIO HDR6 GPIO HDR7 R100 R101 R102 R103 200 200 200 200 5 5 5 5 1 16W 1...

Page 39: ...GPIO_SWITCH_1 LOC E12 NET GPIO_SWITCH_2 LOC F12 NET GPIO_SWITCH_3 LOC V13 NET GPIO_BUTTON0 LOC P4 NET GPIO_BUTTON1 LOC F6 NET GPIO_BUTTON2 LOC E4 NET GPIO_BUTTON3 LOC F5 NET CPU_RESET LOC N4 NET GPIO...

Page 40: ...LED DS15 is illuminated Onboard Power Supplies The diagram in Figure 1 30 shows the power supply architecture and maximum current handling on each supply The typical operating currents are significant...

Page 41: ...1 2V 8A max 1 8V 8A max Linear Regulator LT1763 Monolithic Regulator 0 9V 3A max Buck Boost Regulator LT1731 12V 1A max 3 0V 500mA max UG518_30 _070809 Table 1 22 Estimated Current Draw Rail V Estima...

Page 42: ...at any time under any mode pin setting JTAG initiated configuration takes priority over the mode pin settings FMC bypass jumper J4 must be connected between pins 1 2 for JTAG access to the FPGA on the...

Page 43: ...FPGA The iMPACT software tool can also program the SPI x4 flash or the BPI flash via the USB J10 connection iMPACT can download a temporary design to the FPGA through the JTAG This provides a connecti...

Page 44: ...44 www xilinx com SP601 Hardware User Guide UG518 v1 1 August 19 2009 Chapter 1 SP601 Evaluation Board...

Page 45: ...ee www xilinx com support documentation index htm Documents supporting the SP601 Evaluation Board 1 UG138 LogiCORE IP Tri Mode Ethernet MAC v4 2 User Guide 2 UG380 Spartan 6 FPGA Configuration User Gu...

Page 46: ...46 www xilinx com SP601 Hardware User Guide UG518 v1 1 August 19 2009 Appendix A References...

Page 47: ...per and switch settings for the SP601 Table B 1 Default Jumper and Switch Settings REFDES Type Function Default SW1 SLIDE POWER ON OFF OFF SW2 DIP 2 POLE MODE 1 M0 ON 1 2 M1 OFF 0 SW8 DIP 4 POLE GPIO...

Page 48: ...48 www xilinx com SP601 Hardware User Guide UG518 v1 1 August 19 2009 Appendix B Default Jumper and Switch Settings...

Page 49: ...14 C18 FMC_LA14_P B2 D12 FMC_LA05_N A14 C19 FMC_LA14_N A2 D14 FMC_LA09_P G11 C22 FMC_LA18_CC_P R10 D15 FMC_LA09_N F10 C23 FMC_LA18_CC_N T10 D17 FMC_LA13_P B11 C26 FMC_LA27_P R11 D18 FMC_LA13_N A11 C27...

Page 50: ...H22 FMC_LA19_P N6 G24 FMC_LA22_P R7 H23 FMC_LA19_N P7 G25 FMC_LA22_N T7 H25 FMC_LA21_P T4 G27 FMC_LA25_P M11 H26 FMC_LA21_N V4 G28 FMC_LA25_N N11 H28 FMC_LA24_P U8 G30 FMC_LA29_P M8 H29 FMC_LA24_N V8...

Page 51: ...A3 LOC L7 NET DDR2_A4 LOC F3 NET DDR2_A5 LOC H4 NET DDR2_A6 LOC H3 NET DDR2_A7 LOC H6 NET DDR2_A8 LOC D2 NET DDR2_A9 LOC D1 NET DDR2_A10 LOC F4 NET DDR2_A11 LOC D3 NET DDR2_A12 LOC G6 NET DDR2_BA0 LOC...

Page 52: ...G13 NET FLASH_A17 LOC H12 NET FLASH_A18 LOC D18 NET FLASH_A19 LOC D17 NET FLASH_A20 LOC G14 NET FLASH_A21 LOC F14 NET FLASH_A22 LOC C18 NET FLASH_A23 LOC C17 NET FLASH_A24 LOC F16 NET FLASH_CE_B LOC...

Page 53: ...OC P7 NET FMC_LA19_P LOC N6 NET FMC_LA20_N LOC P8 NET FMC_LA20_P LOC N7 NET FMC_LA21_N LOC V4 NET FMC_LA21_P LOC T4 NET FMC_LA22_N LOC T7 NET FMC_LA22_P LOC R7 NET FMC_LA23_N LOC P6 NET FMC_LA23_P LOC...

Page 54: ...IO_BUTTON2 LOC E4 NET GPIO_BUTTON3 LOC F5 NET GPIO_HDR0 LOC N17 NET GPIO_HDR1 LOC M18 NET GPIO_HDR2 LOC A3 NET GPIO_HDR3 LOC L15 NET GPIO_HDR4 LOC F15 NET GPIO_HDR5 LOC B4 NET GPIO_HDR6 LOC F13 NET GP...

Page 55: ...C G8 NET PHY_TXD2 LOC A6 NET PHY_TXD3 LOC B6 NET PHY_TXD4 LOC E6 NET PHY_TXD5 LOC F7 NET PHY_TXD6 LOC A5 NET PHY_TXD7 LOC C5 NET PHY_TXER LOC A8 NET SMACLK_N LOC H18 NET SMACLK_P LOC H17 NET SPI_CS_B...

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