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ML623 Board User Guide
UG724 (v1.1) September 15, 2010
Chapter 1:
ML623 Board Features and Operation
Differential SMA Global Clock Inputs
[
Figure 1-2
, callout
12
]
The ML623 board provides two pairs of differential SMA transceiver clock inputs that can
be used for connecting to an external function generator. The FPGA clock pins are
connected to the SMA connectors as shown in
Table 1-7
.
SuperClock-2 Module
[
Figure 1-2
, callout
13
]
The SuperClock-2 module connects to the clock module interface connector (J32) and
provides a programmable, low-noise clock source for the ML623 board. The clock module
maps to FPGA I/O by way of 24 control pins, 3 LVDS pairs, 1 regional clock pair, and 1
reset pin.
Table 1-8
shows the FPGA I/O mapping for the SuperClock-2 module interface.
The ML623 board also supplies 5V, 3.3V, and 2.5V input power to the clock module
interface.
Table 1-6:
Single-Ended SMA Clock Connections
FPGA Pin
Net Name
SMA Connector
H28
CLK_A
J171
K24
CLK_B
J172
Table 1-7:
Differential SMA Clock Connections
FPGA Pin
Net Name
SMA Connector
B31
CLK_DIFF_A_P
J167
A31
CLK_DIFF_A_N
J168
L23
CLK_DIFF_B_P
J169
M22
CLK_DIFF_B_N
J170
Table 1-8:
SuperClock-2 FPGA I/O Mapping
FPGA Pin
Net Name
J32 Pin
J17
CM_LVDS1_P
1
J16
CM_LVDS1_N
3
K18
CM_LVDS2_P
9
K17
CM_LVDS2_N
11
E16
CM_LVDS3_P
17
D16
CM_LVDS3_N
19
A16
CM_GCLK_P
25
B16
CM_GCLK_N
27
C18
CM_CTRL_0
61
B18
CM_CTRL_1
63
