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ML623 Board User Guide
UG724 (v1.1) September 15, 2010
Chapter 1:
ML623 Board Features and Operation
Technology Module is installed, place jumpers on JP1 and/or JP2 across pins 2–3 (OFF
position).
Note:
The power regulation jumper must be placed in the OFF position before connecting an
external supply to its corresponding supply jack.
The Texas Instruments and Intersil modules do not have voltage regulation jumpers and
must
be removed from the board before providing external power to the GTX transceiver
rails.
Caution!
The Intersil module features an MGTAVCC voltage adjust header, J1. Make sure to
remove any jumper across J1 before powering the board with the Intersil module installed. Failure to
do so may damage the FPGA.
FPGA Configuration
[
Figure 1-2
, callout
2
]
The FPGA is configured in JTAG mode only using one of the following options:
•
Platform Cable USB
•
Parallel Cable IV
•
Parallel Cable III
•
System ACE controller
Detailed information on the System ACE controller is available in
DS080
,
System ACE CompactFlash Solution
.
The FPGA is configured through one of the aforementioned cables by connecting the cable
to the download cable connector, J1.
The FPGA is configured through the System ACE controller by setting the 3-bit
configuration address DIP switches (SW3) to select one of eight bitstreams stored on a
CompactFlash memory card (see
Configuration Address DIP Switches, page 16
).
Note:
The System ACE controller is bypassed when the flying wire leads or the Parallel Cable IV
cable is used, causing no disruption in the JTAG chain.
The JTAG chain of the board is illustrated in
Figure 1-5
(the four System ACE interface
isolation jumpers described in
JTAG Isolation Jumpers
are not shown). Shorting pins 1–2
on header J162 automatically bypasses the FMC modules and the GTX transceiver power
supply module in the chain.
