Xilinx ML605, Hardware Tutorial

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32 www.xilinx.com ML605/SP605 Hardware Tutorial
UG669 (v3.0) March 15, 2011
System Design Flow
2. For S_AXI_LITE , click on the No Connection box. The Connection Dialog box
appears. In the left column select AXI_Lite interconnect (see Figure 19 ).
3. Click OK .
Connecting the Bus Interfaces of the PERF_AXI_Central_DMA Core
1. Expand the PERF_AXI_Central_DMA core in the System Assembly View (SAV) of the
XPS GUI by clicking the respective + .
2. For
S_AXI
, click on the
No Connection
box. The Connection Dialog box appears. In
the left column select
AXI_Lite
interconnect.
3. Click
OK
.
Connecting the Crossbar for AXI_CDMA Master
The AXI interconnect allows for sparse crossbar which is different from the shared bus
methodology (all masters have access to all slaves).
• For the ML605 system, the AXI_CDMA master is connected to the AXI_MM
interconnect. The master only accesses the DDR3_SDRAM memory. The AXI_CDMA
master does not have access to Internal_Bram or Flash, which are also connected to
the AXI_MM interconnect.
• For the SP605 system, the AXI_CDMA master is connected to AXI_DMA_MM
(connected to third port on the MCB).
1. Expand the DDR3_SDRAM core in the System Assembly View of the XPS GUI by
clicking the respective + .
• For ML605:
For S_AXI , click on the row under the Bus Name column. The Connection Dialog
box appears. In the left column select the AXI_MM interconnect. In the right
column select the box for AXI_Central_DMA.M_AXI .
X-Ref Target - Figure 19
Figure 19: Connecting AXI_Central_DMA Slave Interface
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