Ethernet 1000BASE-X PCS/PMA or SGMII v7.0
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49
UG145 January 18, 2006
SGMII Example Design / Dynamic Switching Example Design
R
Demonstration Test Bench
Figure 4-12
illustrates the demonstration test bench for the Ethernet 1000BASE-X
PCS/PMA or SGMII Core in SGMII mode.
The demonstration test bench is described in the following files:
VHDL
project_dir>
/
<component_name>
/simulation/
demo_tb.vhd
Verilog
project_dir>
/
<component_name>
/simulation/
demo_tb.v
The demonstration test bench is a simple VHDL or Verilog program to exercise the
example design and the core itself. The demonstration test bench performs the following
tasks.
•
Input clock signals are generated.
•
A reset is applied to the example design.
•
The Ethernet 1000BASE-X PCS/PMA core is configured through the MDIO interface
by injecting an MDIO frame into the example design. This disables Auto-Negotiation
and takes the core out of Isolate state.
•
The following frames are injected into the GMII transmitter by the GMII stimulus
block at 1 Gbps.
Figure 4-12:
Demonstration Test Bench for the Ethernet 1000BASE-X PCS/PMA or
SGMII Core in SGMII Mode
PMA
Monitor
(serial to parallel
conversion and
8B10B
decoding)
PMA
Stimulus
(8B10B encoding
and parallel to
serial
conversion)
GMII
Stimulus
GMII
Monitor
GMII
RocketIO
DUT
Demonstration Testbench
Control and data structures
Configuration
Stimulus
