Xilinx LogiCORE MicroBlaze Product Manual Download Page 32

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MicroBlaze Micro Controller System v1.3

www.xilinx.com

PG048 December 18, 2012

Chapter 4:

Customizing and Generating the Core

- In Vivado or PlanAhead this file is typically called

project-name.runs/

impl_1/toplevel.bit

- In Project Navigator this file is typically called

toplevel.bit

Click the second

Browse

button, and navigate to the BMM file updated with block

RAM placement.
- In Vivado this file is typically called

project-name.runs/impl_1/

toplevel_bd.bmm

- In PlanAhead with one MicroBlaze MCS component, this file is typically called

project-name.srcs/sources_1/ip/component-name/

component_name_bd.bmm.

With more than one MicroBlaze MCS component,

the merged BMM file updated with block RAM placement must be selected

instead.

- In Project Navigator with one MicroBlaze MCS component, this file is typically

called

ipcore_dir/component_name_bd.bmm

. With more than one

MicroBlaze MCS component, the merged BMM file updated with block RAM

placement must be selected instead.

Click

Program

to perform the import and program the FPGA.

For additional information, see the

Xilinx SDK Help

[Ref 6]

Summary of Contents for LogiCORE MicroBlaze

Page 1: ...LogiCORE IP MicroBlaze Micro Controller System v1 3 Product Guide PG048 December 18 2012...

Page 2: ...ification Standards Compliance 7 Performance 7 Resource Utilization 8 Port Descriptions 9 Register Space 10 Chapter 3 Designing with the Core General Design Guidelines 11 Clocking 11 Resets 12 Protoco...

Page 3: ...e Core GUI 35 Parameter Values 43 Parameter Port Dependencies 43 Tool Flow 43 Chapter 7 Constraining the Core Clock Management 51 SECTION IV APPENDICES Appendix A Application Software Development Xili...

Page 4: ...MicroBlaze Micro Controller System v1 3 www xilinx com 3 PG048 December 18 2012 SECTION I SUMMARY IP Facts Overview Product Specification Designing with the Core...

Page 5: ...Core Specifics Supported Device Family 1 Zynq 7000 2 Virtex 7 Kintex 7 Artix 7 Virtex 6 Virtex 5 Spartan 6 Virtex 4 Spartan 3 Supported User Interfaces Local Memory Bus LMB Dynamic Reconfiguration Por...

Page 6: ...nstruction set computer RISC optimized for implementation in Xilinx Field Programmable Gate Arrays FPGAs Detailed information on the MicroBlaze processor can be found in the MicroBlaze Processor Refer...

Page 7: ...M data sheet Ref 3 The MDM parameters except the JTAG user defined register are fixed and their values can be found in Table 4 8 When more than one MicroBlaze MCS instance with debug enabled is includ...

Page 8: ...are aligned to MicroBlaze targets as well as the access latency optimized for MicroBlaze data access Maximum Frequencies The following are clock frequencies for the target families The maximum achieva...

Page 9: ...ates and the actual utilization of FPGA resources and timing of the MicroBlaze MCS design will vary from the results reported here All parameters not given in Table 2 2 have their default values Table...

Page 10: ...value Trace_Jump_Taken O Branch instruction evaluated TRUE taken Trace_Delay_Slot O Instruction is in delay slot of a taken branch Trace_Data_AccessT O Valid D side memory access Trace_Data_Address 0...

Page 11: ...d PITx_Toggle when PITx lapses GPO Signals GPOx 1 C_GPOx_SIZE 1 0 O GPOx Output GPI Signals GPIx 1 C_GPIx_SIZE 1 0 I GPIx Input GPIx_Interrupt 1 O GPIx input changed INTC Signals INTC_Interrupt 0 C_IN...

Page 12: ...ose Input and Interrupt Controller All of these interfaces are directly connected to the I O Module inside the MicroBlaze MCS MicroBlaze Trace Signals See the MicroBlaze Processor Reference Guide Ref...

Page 13: ...Reset input is the master reset input signal for the entire MicroBlaze MCS In addition the entire MicroBlaze MCS or just the MicroBlaze processor can be reset from the Xilinx MicroProcessor Debugger...

Page 14: ...MicroBlaze Micro Controller System v1 3 www xilinx com 13 PG048 December 18 2012 SECTION II VIVADO DESIGN SUITE Customizing and Generating the Core Constraining the Core...

Page 15: ...Core This chapter includes information on using Xilinx tools to customize and generate the core using the Vivado Design Suite GUI MicroBlaze MCS parameters are divided in seven tabs MCS UART FIT PIT...

Page 16: ...port When debug support is enabled it is possible to debug software via JTAG from Xilinx Software Development Kit SDK or directly using the Xilinx Microprocessor Debugger XMD Debug JTAG User defined R...

Page 17: ...s Defines the number of data bits used by the UART Should almost always be set to 8 Use Parity Enable this parameter to use parity checking of the UART characters Even or Odd Parity Select odd or even...

Page 18: ...arameter tab showing the parameters for one of the four timers is shown in Figure 4 3 Use FIT Enable the Fixed Interval Timer Number of Clocks Between Strobes The number of clock cycles between each s...

Page 19: ...ammable Interval Timer counter is readable by software when this parameter is set RECOMMENDED Unless resource usage is critical it is recommended that you keep this enabled Define Prescaler Selects a...

Page 20: ...Purpose Output ports is shown in Figure 4 5 Use GPO Enable the General Purpose Output port Number of Bits Set the number of bits of the General Purpose Output port Initial Value of GPO Set the initia...

Page 21: ...ab showing the parameters for one of the four General Purpose Input ports is shown in Figure 4 6 Use GPI Enable the General Purpose Input port Number of Bits Set the number of bits of the General Purp...

Page 22: ...ach bit in the value corresponds to the equivalent interrupt input When a bit is set to one the interrupt is edge triggered otherwise it is level sensitive Positive or Negative External Interrupts Set...

Page 23: ...d Table 4 7 LMB BRAM IF Controller Table 4 8 MicroBlaze Debug Module Table 4 1 MicroBlaze MCS Parameters Parameter Name Feature Description Allowable Values Default Value VHDL Type MCS Parameters C_FA...

Page 24: ...sed determines whether parity is odd or even 0 Even Parity 1 Odd Parity 0 integer C_UART_RX_INTERRUPT Use UART RX Interrupt in INTC 0 Not Used 1 Used 0 integer C_UART_TX_INTERRUPT Use UART TX Interrup...

Page 25: ...Ix_INTERRUPT 2 Use GPIx_Interrupt in INTC 0 Not Used 1 Used 0 integer INTC Parameters C_INTC_USE_EXT_INTR Use I O Module external interrupt inputs 0 Not Used 1 Used 0 integer C_INTC_INTR_SIZE Number o...

Page 26: ...er 0x00 C_INSTANCE Instance Name Value of MicroBlaze MCS parameter C_MICROBLAZE_INSTANCE C_D_PLB Data side PLB interface All other data side PLB parameters are don t care 0 C_D_AXI Data side AXI inter...

Page 27: ...0 C_USE_DCACHE Data cache All other data cache parameters are don t care 0 C_USE_MMU Memory management All other MMU parameters are don t care 0 C_USE_INTERRUPT Enable interrupt handling 2 C_USE_EXT_...

Page 28: ...B data bus width 32 C_EXT_RESET_HIGH Level of external reset 1 active High reset Table 4 5 Internal LMB_v10 Parameters Settings DLMB Parameter Name Feature Description Value C_LMB_NUM_SLAVES Number of...

Page 29: ...000000 C_LMB_AWIDTH LMB address bus width 32 C_LMB_DWIDTH LMB data bus width 32 C_ECC Implement error correction and detection All other ECC as well as AXI and PLB parameters are don t care 0 No ECC T...

Page 30: ...The generic tool flow in Vivado is shown in Figure 4 8 X Ref Target Figure 4 8 Figure 4 8 Generic Vivado Tool Flow Add IP Implement Project Import Hardware Description Import Hardware Create Software...

Page 31: ...directory project name runs impl_1 For additional information see the Xilinx Vivado Manuals Ref 9 SDK The SDK commands to achieve the MicroBlaze MCS specific steps above are detailed here Import Hardw...

Page 32: ...1 toplevel_bd bmm In PlanAhead with one MicroBlaze MCS component this file is typically called project name srcs sources_1 ip component name component_name_bd bmm With more than one MicroBlaze MCS com...

Page 33: ...de Selections There are no Device Package or Speed Grade requirements for this core Clock Frequencies There are no specific clock frequency requirements for this core Clock Management MicroBlaze MCS i...

Page 34: ...com 33 PG048 December 18 2012 Chapter 5 Constraining the Core Transceiver Placement There are no Transceiver Placement requirements for this core I O Standard and Placement There are no specific I O...

Page 35: ...MicroBlaze Micro Controller System v1 3 www xilinx com 34 PG048 December 18 2012 SECTION III ISE DESIGN SUITE Customizing and Generating the Core Constraining the Core...

Page 36: ...GUI The I O Module parameters are divided in seven tabs MCS UART FIT PIT GPO GPI and Interrupts The MCS parameter tab is shown in Figure 6 1 Instance Hierarchical Design Name Defines the unique instan...

Page 37: ...ia JTAG from Xilinx Software Development Kit SDK or directly using the Xilinx Microprocessor Debugger XMD Debug JTAG User defined Register Specifies the JTAG user defined register for debug When more...

Page 38: ...ys be set to 8 Use Parity Enable this parameter to use parity checking of the UART characters Even or Odd Parity Select odd or even parity Only available when parity is used Implement Receive Interrup...

Page 39: ...arameter tab showing the parameters for one of the four timers is shown in Figure 6 3 Use FIT Enable the Fixed Interval Timer Number of Clocks Between Strobes The number of clock cycles between each s...

Page 40: ...ammable Interval Timer counter is readable by software when this parameter is set RECOMMENDED Unless resource usage is critical it is recommended that you keep this enabled Define Prescaler Selects a...

Page 41: ...pose Output ports enabled is shown in Figure 6 5 Use GPO Enable the General Purpose Output port Number of Bits Set the number of bits of the General Purpose Output port Initial Value of GPO Set the in...

Page 42: ...howing the parameters with one of the four General Purpose Input ports enabled is shown in Figure 6 6 Use GPI Enable the General Purpose Input port Number of Bits Set the number of bits of the General...

Page 43: ...ach bit in the value corresponds to the equivalent interrupt input When a bit is set to one the interrupt is edge triggered otherwise it is level sensitive Positive or Negative External Interrupts Set...

Page 44: ...ons detailed in Table 4 2 MicroBlaze Table 4 3 I O Module Table 4 4 and Table 4 5 LMB v10 Table 4 6 and Table 4 7 LMB BRAM IF Controller Table 4 8 MicroBlaze Debug Module Parameter Port Dependencies T...

Page 45: ...eters are defined using the configuration dialog and the component is generated and synthesized Several files are created during this step X Ref Target Figure 6 8 Figure 6 8 Generic PlanAhead and Proj...

Page 46: ...y find all the MicroBlaze MCS core BMM files in the project and merge them using a text editor The contents of the files can be concatenated in any order except that the id number at the end of each A...

Page 47: ...t the bitstream can be updated with software after it has been generated Update Bitstream with Software This step is used to update the previously generated bitstream with all software executable file...

Page 48: ...script provided to perform the steps Create Merged BMM and Update Tool to Use BMM In the Tcl Console type the following commands cd project path source project name srcs sources_1 ip component name mi...

Page 49: ...runs impl_1 toplevel bit o b project name runs impl_1 download bit Here part is the complete part name consisting of device package and speed concatenated With more than one MicroBlaze MCS component...

Page 50: ...ith Software and Generate Simulation Files Type the following command in the Tcl Console to perform this with one MicroBlaze MCS component microblaze_mcs_data2mem sdk workspace path sdk program Debug...

Page 51: ...than one MicroBlaze MCS component the bm option must indicate the merged BMM file updated with block RAM placement For each additional MicroBlaze MCS component the bd option has to be repeated follow...

Page 52: ...ze Micro Controller System v1 3 www xilinx com 51 PG048 December 18 2012 Chapter 7 Constraining the Core Clock Management MicroBlaze MCS is fully synchronous with all clocked elements clocked by the C...

Page 53: ...MicroBlaze Micro Controller System v1 3 www xilinx com 52 PG048 December 18 2012 SECTION IV APPENDICES Application Software Development Debugging Additional Resources...

Page 54: ...Software Development Kit MicroBlaze MCS can be used with the Xilinx Software Development Kit SDK in the same way as any embedded system The specific steps needed with MicroBlaze MCS are described in...

Page 55: ...the MicroBlaze MCS the Xilinx Support web page www xilinx com support contains key resources such as product documentation release notes answer records information about known issues and links for op...

Page 56: ...oper keywords such as Product name Tool message s Summary of the issue encountered A filter search is available after results are returned to further target the results Answer Records for the MicroBla...

Page 57: ...and virtual I O cores directly into your design The ChipScope Pro debugging tool allows you to set trigger conditions to capture application and integrated block port signals in hardware Captured sign...

Page 58: ...s is case sensitive in the tools The parameter Memory Size set in the MicroBlaze MCS configuration dialog has changed but the corresponding BMM file has not been updated Corrective action Change Insta...

Page 59: ...d BMM filename Please regenerate the MicroBlaze MCS instance ERROR Could not find BMM filename Please invoke microblaze_mcs_setup and implement the design Possible causes With PlanAhead the BMM file h...

Page 60: ...Build with a bm option or embedded BMM information must be included in the source HDL Possible causes The design has been implemented without the Ngdbuild bm option to define the BMM file but with the...

Page 61: ...the MicroBlaze processor with the simulation Use the microblaze_mcs_data2mem Tcl procedure to do this in ISE Project Navigator or PlanAhead The equivalent command in Vivado Design Suite is Tools Asso...

Page 62: ...Ensure that all the timing constraints for the core were properly incorporated from the example design and that all constraints were met during implementation Does it work in post place and route tim...

Page 63: ...umentation see www xilinx com company terms htm References These documents provide supplemental material useful with this user guide 1 Local Memory Bus LMB V10 Product Guide PG087 2 IP Processor LMB B...

Page 64: ...duce modify distribute or publicly display the Materials without prior written consent Certain products are subject to the terms and conditions of the Limited Warranties which can be viewed at http ww...

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