Xilinx LogiCORE IP v1.02a Product Manual Download Page 25

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I/O Module v1.02a

www.xilinx.com

PG052 October 16, 2012

General Design Guidelines

The I/O Bus is fully compatible with the Xilinx Dynamic Reconfiguration Port (DRP). This

configuration port supports partial dynamic reconfiguration of functional blocks, such as

CMTs, clock management, XADC, serial transceivers, and the PCIe® block.

The nominal connection of the I/O Bus to the DRP is shown in

Table 3-2

For a detailed description of the DRP, see the

7 Series FPGAs Configuration User Guide

[Ref 2]

UART

The Universal Asynchronous Receiver Transmitter (UART) interface provides the controller

interface for asynchronous serial data transfers. Features supported include:

• One transmit and one receive channel (full duplex)
• Configurable number of data bits in a character (5-8)
• Configurable parity bit (odd or even)
• Configurable and programmable baud rate

The UART performs parallel-to-serial conversion on characters received through LMB and

serial-to-parallel conversion on characters received from a serial peripheral. The UART is

capable of transmitting and receiving 8, 7, 6 or 5-bit characters, with 1-stop bit and odd,

even or no parity. The UART can transmit and receive independently.

The device can be configured and its status can be monitored via the internal register set.

The UART also asserts the

UART_Interrupt

output when the receiver becomes

non-empty, when the transmitter becomes empty or when an error condition has occurred.

The individual interrupt events are connected to the Interrupt Controller of the I/O Module

and can be used to assert the

INTC_IRQ

output signal.

Table 3-2:

Mapping of the I/O Bus to the Dynamic Reconfiguration Port

MicroBlaze MCS Signal

DRP Signal

Note

Clk

DCLK

IO_Addr_Strobe

DEN

IO_Read_Strobe

Not used by DRP

IO_Write_Strobe

DWE

IO_Address[m+2:2]

DADDR[m:0]

Uses 32-bit word access for DRP

IO_Byte_Enable

Only 32-bit word accesses used for DRP

IO_Write_Data[n:0]

DI[n:0]

Data width depends on DRP (n < 32)

IO_Read_Data[n:0]

DO[n:0]

Data width depends on DRP (n < 32)

IO_Ready

DRDY

Summary of Contents for LogiCORE IP v1.02a

Page 1: ...LogiCORE IP I O Module v1 02a Product Guide PG052 October 16 2012 ...

Page 2: ...ndards 9 Performance 9 Resource Utilization 10 Port Descriptions 11 Register Space 13 Chapter 3 Designing with the Core General Design Guidelines 23 LMB Timing 28 Clocking 28 Resets 28 Protocol Description 29 SECTION II VIVADO DESIGN SUITE Chapter 4 Customizing and Generating the Core GUI 31 Parameter Values 37 Chapter 5 Constraining the Core Required Constraints 40 Device Package and Speed Grade ...

Page 3: ...SUITE Chapter 6 Customizing and Generating the Core GUI 43 Parameter Values 49 Chapter 7 Constraining the Core Clock Management 51 SECTION IV APPENDICES Appendix A Migrating Appendix B Debugging Solution Centers 54 Appendix C Application Software Development Device Drivers 55 Appendix D Additional Resources Xilinx Resources 56 References 56 Technical Support 56 Revision History 57 Notice of Discla...

Page 4: ...I O Module v1 02a www xilinx com 4 PG052 October 16 2012 SECTION I SUMMARY IP Facts Overview Product Specification Designing with the Core ...

Page 5: ...irtex 7 Kintex 7 Artix 7 Virtex 6 Spartan 6 Virtex 5 Virtex 4 Spartan 3 Supported User Interfaces Local Memory Bus LMB Dynamic Reconfiguration Port DRP Resources See Table 2 2 Provided with Core Design Files ISE VHDL Vivado RTL Example Design Not Provided Test Bench Not Provided Constraints File Not Provided Simulation Model VHDL Behavioral Supported S W Driver 3 Standalone Tested Design Flows Des...

Page 6: ...in the MicroBlaze Bus Interfaces chapter in the MicroBlaze Processor Reference Guide Ref 1 In a MicroBlaze system the I O Module would typically be connected according to Figure 1 2 X Ref Target Figure 1 1 Figure 1 1 I O Module Block Diagram I O Module LMB UART_Tx_IO UART_Interrupt FITx_Interrupt PITx_Interrupt GPOx_IO INTC_Interrupt INTC_IRQ IO_Addr_Strobe IO_Read_Strobe IO_Write_Strobe IO_Addres...

Page 7: ...O Bus is fully compatible with the Xilinx Dynamic Reconfiguration Port DRP UART The Universal Asynchronous Receiver Transmitter UART interface provides the controller interface for asynchronous serial data transfers Features supported include One transmit and one receive channel full duplex Configurable number of data bits in a character 5 8 Configurable parity bit odd or even Configurable and pro...

Page 8: ...e Input GPI The General Purpose Input GPI makes it possible for software to sample the value of the I O Module GPI input signals by reading the GPI register The width and whether to generate an interrupt are defined by parameters Interrupt Controller INTC The Interrupt Controller handles both I O module internal interrupt events and external ones The internal interrupt events originate from the UA...

Page 9: ...ed to MicroBlaze targets as well as the access latency optimized for MicroBlaze data access Maximum Frequencies The following are clock frequencies for the target families The maximum achievable clock frequency can vary The maximum achievable clock frequency and all resource counts can be affected by the used tool flow other tool options additional logic in the FPGA using different versions of Xil...

Page 10: ...e just estimates and the actual utilization of FPGA resources and timing of the MicroBlaze MCS design will vary from the results reported here All parameters not given in the table below have their default values Table 2 2 Performance and Resource Utilization Benchmarks on Virtex 6 xc6vlx240t 1 ff1156 Parameter Values other parameters at default value Device Resources C_USE_UART_RX C_USE_UART_TX C...

Page 11: ...B Read Data Bus Sl_Ready O LMB Data Ready Sl_Wait O LMB Wait Sl_CE O LMB Correctable Error Sl_UE O LMB Uncorrectable Error I O Bus Signals IO_Addr_Strobe O Address strobe signals valid I O Bus output signals IO_Read_Strobe O I O Bus access is a read IO_Write_Strobe O I O Bus access is a write IO_Address 31 0 O Address for access IO_Byte_Enable 3 0 O Byte enables for access IO_Write_Data 31 0 O Dat...

Page 12: ...Ix 1 C_GPIx_SIZE 1 0 I GPIx Input GPIx_Interrupt 1 C_GPIx_SIZE 1 0 O GPIx input changed INTC Signals INTC_Interrupt 0 C_INTC_INTR_SIZE 1 I External interrupt inputs INTC_IRQ O Interrupt Output INTC_Interrupt_Address C_INTC_ADDR_WIDTH 1 0 O Interrupt Address Output INTC_Interrupt_Ack 1 0 I Interrupt Acknowledge Input 1 x 1 2 3 or 4 Table 2 4 Parameter Port Dependencies Parameter Name Ports Port wid...

Page 13: ...PI4 R General Purpose Input 4 Register C_BASEADDR 0x30 IRQ_STATUS R Interrupt Status Register C_BASEADDR 0x34 IRQ_PENDING R Pending Interrupt Register C_BASEADDR 0x38 IRQ_ENABLE W Interrupt Enable Register C_BASEADDR 0x3C IRQ_ACK W Interrupt Acknowledge Register C_BASEADDR 0x40 PIT1_PRELOAD W PIT1 Preload Register C_BASEADDR 0x44 PIT1_COUNTER R PIT1 Counter Register C_BASEADDR 0x48 PIT1_CONTROL W ...

Page 14: ...r when the character has not been transmitted will overwrite previously written data resulting in loss of data The register is implemented if C_USE_UART_TX is set to 1 C_BASEADDR 0x80 C_BASEADDR 0xFC IRQ_VECTOR_0 IRQ_VECTOR_31 W Interrupt Address Vector Registers C_BASEADDR 0x100 C_HIGHADDR Reserved C_IO_BASEADDR C_IO_HIGHADDR I O Bus RW Mapped to I O Bus address output IO_Address Table 2 6 UART R...

Page 15: ...0 No parity error has occurred 1 A parity error has occurred 6 Frame Error R 0 Indicates that a frame error has occurred after the last time the status register was read Frame Error is defined as detection of a stop bit with the value 0 The receive character is ignored and not written to the receive register This bit is cleared when the status register is read 0 No Frame error has occurred 1 A fra...

Page 16: ...x 1 2 3 or 4 This register reads the value that is input on the corresponding I O Module GPIx port input signal bits This register is not implemented if the value of C_USE_GPIx is 0 Table 2 12 UART Programmable Baud Rate Register UART_BAUD Reserved UART_BAUD 31 20 19 0 Table 2 13 UART Programmable Baud Rate Register Bit Definitions Bit s Name Core Access Reset Value Description 31 20 Reserved 19 0...

Page 17: ...d INTC_Interrupt Reserved Internal Interrupts 31 C_INTC_EXT_INTR 16 C_INTC_EXT_INTR 15 16 15 11 10 0 Table 2 19 Interrupt Status Register Bit Definitions Bit s Name Core Access Reset Value Description 31 C_INTC_EXT_INTR 16 R 0 Reserved C_INTC_EXT_INTR 15 16 INTC_Interrupt R 0 I O Module external interrupt input signal INTC_Interrupt C_INTC_EXT_INTR 1 0 mapped to corresponding bit positions in IRQ_...

Page 18: ...16 C_INTC_EXT_INTR 15 16 15 11 10 0 Table 2 21 Interrupt Pending Register Bit Definitions Bit s Name Core Access Reset Value Description 31 C_INTC_EXT_INTR 16 R 0 Reserved C_INTC_EXT_INTR 15 16 INTC_Interrupt R 0 I O Module external interrupt input signal INTC_Interrupt C_INTC_EXT_INTR 1 0 mapped to corresponding bit positions in IRQ_STATUS 15 R 0 Reserved 14 GPI4 R 0 GPI4 changed 13 GPI3 R 0 GPI3...

Page 19: ... Interrupt Enable Register Bit Definitions Bit s Name Core Access Reset Value Description 31 C_INTC_EXT_INTR 16 0 Reserved C_INTC_EXT_INTR 15 16 INTC_Interrupt W 0 Enable I O Module external interrupt input signal INTC_Interrupt 16 C_INTC_EXT_INTR 15 0 Reserved 14 GPI4 R 0 GPI4 changed 13 GPI3 R 0 GPI3 changed 12 GPI2 R 0 GPI2 changed 11 GPI1 R 0 GPI1 changed 10 FIT4 W 0 FIT4 interrupt enabled 9 F...

Page 20: ...t to 1 use fast interrupt mode The register is write only The register is only implemented when fast interrupt mode is enabled by setting C_INTC_HAS_FAST to 1 Table 2 24 Interrupt Acknowledge Register IRQ_ACK IRQ_ACK 31 0 Table 2 25 Interrupt Acknowledge Register Bit Definitions Bit s Name Core Access Reset Value Description 31 0 IRQ_ACK W 0 All bit position written with 1 will clear corresponding...

Page 21: ...e is enabled by setting C_INTC_HAS_FAST to 1 PITx Preload Register PITx_PRELOAD x 1 2 3 or 4 The value written to this register determines the period between two consecutive PITx_Interrupt events The period is the value written to the register 2 count events The register is implemented if C_USE_PITx is 1 Table 2 28 Interrupt Address Vector Register IRQ_VECTOR_x 0 IRQ_VECTOR_x 0 31 C_INTC_ADDR_WIDT...

Page 22: ...ting the number of cycles defined in PITx_PRELOAD The register is implemented if C_USE_PITx is 1 Table 2 32 PITx Counter Register PITx_COUNTER Reserved PITx_PRELOAD 31 C_PITx_SIZE C_PITx_SIZE 1 31 Table 2 33 PITx Counter Register Bit Definitions Bit s Name Core Access Reset Value Description 31 C_PITx_SIZE Reserved C_PITx_SIZE 1 0 PITx_COUNTER R 0 PITx counter value at time of read Table 2 34 PITx...

Page 23: ...roBlaze Load Store instructions I O Bus data is 32 bit wide with byte enables to write byte and half word data The I O Bus has a ready handshake to handle different waitstate needs from IO_Ready asserted the cycle after the IO_Addr_Strobe is asserted to as many cycles as needed There is no timeout on the I O Bus and MicroBlaze is stalled until IO_Ready is asserted IO_Address IO_Byte_Enable IO_Writ...

Page 24: ...byte and halfword accesses are correctly decoded independent of MicroBlaze endianess X Ref Target Figure 3 1 Figure 3 1 I O Bus Write X Ref Target Figure 3 2 Figure 3 2 I O Bus Read Table 3 1 Valid Values for IO_Byte_Enable 3 0 IO_Byte_Enable IO_Data_Write and IO_Data_Read Byte Lanes Used 3 0 31 24 23 16 15 8 7 0 0001 l 0010 l 0100 l 1000 l 0011 l l 1100 l l 1111 l l l l Clk IO_Address IO_Byte_Ena...

Page 25: ...ters received through LMB and serial to parallel conversion on characters received from a serial peripheral The UART is capable of transmitting and receiving 8 7 6 or 5 bit characters with 1 stop bit and odd even or no parity The UART can transmit and receive independently The device can be configured and its status can be monitored via the internal register set The UART also asserts the UART_Inte...

Page 26: ... mode where the timer reloads automatically when it lapses In continuous mode the period between two PITx_Interrupt assertions is the value in PITx Preload Register 2 count events The PIT can also be used in one shot mode where the timer stops when it has reached zero The timer is implemented by means of a counter that is pre loaded with the timer value and then decremented When the counter reache...

Page 27: ...from the UART the Fixed Interval Timers the Programmable Interval Timers or the General Purpose Inputs For an internal interrupt to be generated on the INTC_IRQ output the corresponding I O Module parameter needs to be set for example C_UART_RX_INTERRUPT 1 and that particular interrupt needs to be enabled in the Interrupt Enable Register The Interrupt Controller supports up to 16 external interrup...

Page 28: ...rt The processor sends 0b01 on this port when the interrupt is being acknowledged by the processor that is when branching to the interrupt service routine sends 0b10 when executing a return from interrupt instruction in the interrupt service routine and sends 0b11 when interrupts are re enabled The bit in IRQ_STATUS corresponding to the interrupt is cleared when 0b10 or 0b11 is seen on the port Wi...

Page 29: ...I O Module v1 02a www xilinx com 29 PG052 October 16 2012 Protocol Description Protocol Description See LMB Interface Description timing diagrams in the MicroBlaze Processor Reference Guide Ref 1 ...

Page 30: ...I O Module v1 02a www xilinx com 30 PG052 October 16 2012 SECTION II VIVADO DESIGN SUITE Customizing and Generating the Core Constraining the Core ...

Page 31: ...uite GUI The I O Module parameters are divided in seven tabs System UART FIT Timers PIT Timers GPO GPI and Interrupt When using Vivado IP Integrator the addresses and masks are auto generated The System tab is shown in Figure 4 1 I O Module Register Base Address Base address of the internal registers I O Module Register High Address High address of the internal registers X Ref Target Figure 4 1 Fi...

Page 32: ...decoding an I O Bus access The UART parameter tab is shown in Figure 4 2 Enable Receiver Enables UART receiver for character input This is automatically connected to standard input stdin in the software program Enable Transmitter Enables UART transmitter for character output This is automatically connected to standard output stdout in the software program Define Baud Rate Sets the UART baud rate T...

Page 33: ...character When the interrupt is not enabled the UART must be polled to wait until data has been transmitted Implement Error Interrupt Generate an interrupt if an error occurs when the UART receives a character This error can be a framing error an overrun error or a parity error if parity is used When the interrupt is not enabled the UART must be polled to check if an error has occurred after a cha...

Page 34: ...less resource usage is very critical it is recommended to keep this enabled Define Prescaler Selects a prescaler as source for the Programmable Interval Timer count When no prescaler is selected the core input clock is used Any Programmable Interval Timer or Fixed Interval Timer can be used as prescaler as well as a dedicated external enable input Generate Interrupt Generate an interrupt when the ...

Page 35: ...pose Output port Initial Value of GPO Set the initial value of the General Purpose Output port The right most bit in the value is assigned to bit 0 of the port the next right most to bit 1 and so on The GPI parameter tab showing the parameters for one of the four General Purpose Input ports is shown in Figure 4 6 X Ref Target Figure 4 5 Figure 4 5 GPO Parameter Tab ...

Page 36: ... General Purpose Input port Number of Bits Set the number of bits of the General Purpose Input port Generate Interrupt Generate an interrupt when a General Purpose Input changes The Interrupt parameter tab is shown in Figure 4 7 X Ref Target Figure 4 6 Figure 4 6 GPI Parameter Tab ...

Page 37: ...or level sensitive interrupts and rising or falling edge for edge triggered interrupts Each bit in the value corresponds to the equivalent interrupt input When a bit is set to one high level or rising edge is used otherwise low level or falling edge is used Use Low latency Interrupt Handling Enable the use of low latency interrupt handling Parameter Values To obtain an I O Module that is uniquely ...

Page 38: ...USE_PARITY Determines whether parity is used or not 0 No Parity 1 Use Parity 0 integer C_UART_ODD_PARITY If parity is used determines whether parity is odd or even 0 Even Parity 1 Odd Parity 0 integer C_UART_RX_INTERRUPT Use UART RX Interrupt in INTC 0 Not Used 1 Used 0 integer C_UART_TX_INTERRUPT Use UART TX Interrupt in INTC 0 Not Used 1 Used 0 integer C_UART_ERROR_ INTERRUPT Use UART ERROR Inte...

Page 39: ... Used 0 integer C_INTC_INTR_SIZE Number of external interrupt inputs used 1 16 1 integer C_INTC_LEVEL_EDGE Level or edge triggered for each external interrupt For each bit 0 Level 1 Edge level std_logic_vector C_INTC_POSITIVE Polarity for each external interrupt For each bit 0 active Low 1 active High active High std_logic_vector C_INTC_HAS_FAST Use fast interrupt mode 0 Not Used 1 Used 0 integer ...

Page 40: ...vice Package or Speed Grade requirements for this core Clock Frequencies There are no specific clock frequency requirements for this core Clock Management The I O Module is fully synchronous with all clocked elements clocked by the Clk input To operate properly when connected to MicroBlaze the Clk must be the same as the MicroBlaze Clk Clock Placement There are no specific Clock placement requirem...

Page 41: ...12 Banking Banking There are no specific Banking rules for this core Transceiver Placement There are no Transceiver Placement requirements for this core I O Standard and Placement There are no specific I O standards and placement requirements for this core ...

Page 42: ...I O Module v1 02a www xilinx com 42 PG052 October 16 2012 SECTION III ISE DESIGN SUITE Customizing and Generating the Core Constraining the Core ...

Page 43: ...in the ISE Design Suite GUI The I O Module parameters are divided in seven tabs System UART FIT Timers PIT Timers GPO GPI and Interrupt The System tab showing the Addresses parameters is shown in Figure 6 1 I O Module Register Base Address Base address of the internal registers I O Module Register High Address High address of the internal registers X Ref Target Figure 6 1 Figure 6 1 System Tab ...

Page 44: ...Decode Mask A mask indicating which address bits the module takes into account when decoding an I O Bus access The UART parameter tab is shown in Figure 6 2 Enable Receiver Enables UART receiver for character input This is automatically connected to standard input stdin in the software program Enable Transmitter Enables UART transmitter for character output This is automatically connected to stand...

Page 45: ...he interrupt is not enabled the UART must be polled to check if data has been received Implement Transmit Interrupt Generate an interrupt when the UART has sent a character When the interrupt is not enabled the UART must be polled to wait until data has been transmitted Implement Error Interrupt Generate an interrupt if an error occurs when the UART receives a character This error can be a framing...

Page 46: ...le Interval Timer counter is readable by software when this parameter is set Unless resource usage is very critical it is recommended to keep this enabled Define Prescaler Selects a prescaler as source for the Programmable Interval Timer count When no prescaler is selected the core input clock is used Any Programmable Interval Timer or Fixed Interval Timer can be used as prescaler as well as a ded...

Page 47: ...pose Output port Initial Value of GPO Set the initial value of the General Purpose Output port The right most bit in the value is assigned to bit 0 of the port the next right most to bit 1 and so on The GPI parameter tab showing the parameters for one of the four General Purpose Input ports is shown in Figure 6 6 X Ref Target Figure 6 5 Figure 6 5 GPO Parameter Tab ...

Page 48: ...012 GUI Use GPI Enable the General Purpose Input port Number of Bits Set the number of bits of the General Purpose Input port Generate Interrupt Generate an interrupt when a General Purpose Input changes X Ref Target Figure 6 6 Figure 6 6 GPI Parameter Tab ...

Page 49: ...ues To allow the user to obtain an I O Module that is uniquely tailored a specific system certain features can be parameterized in the I O module design This allows the user to configure a design that only utilizes the resources required by the system and operates with the best possible performance The specific features that can be parameterized in Xilinx I O Module EDK designs are shown in Table ...

Page 50: ...decode mask 3 0x00800000 std_logic_vector C_IO_HIGHADD R LMB I O Module I O Bus Base Address Valid Address Range 2 0xFFFFFFFF std_logic_vector C_IO_LOWADDR LMB I O Module I O Bus Address Valid Address Range 2 0x00000000 std_logic_vector C_IO_MASK LMB I O Module I O Bus Address Space Decode Mask Valid decode mask 3 0x00800000 std_logic_vector C_LMB_AWIDTH LMB Address Bus Width 32 32 integer C_LMB_D...

Page 51: ...tober 16 2012 Chapter 7 Constraining the Core Clock Management The I O Module is fully synchronous with all clocked elements clocked by the Clk input To operate properly when connected to MicroBlaze the Clk must be the same as the MicroBlaze Clk ...

Page 52: ...I O Module v1 02a www xilinx com 52 PG052 October 16 2012 SECTION IV APPENDICES Migrating Debugging Application Software Development Additional Resources ...

Page 53: ...October 16 2012 Appendix A Migrating This appendix describes migrating from older versions of the IP to the current IP release For information on migrating to the Vivado Design Suite see the Vivado Design Suite Migration Methodology Guide Ref 3 ...

Page 54: ...000 August 10 2012 Appendix B Debugging Solution Centers See the Xilinx Solution Centers for support on devices software tools and intellectual property at all stages of the design cycle Topics include design assistance advisories and troubleshooting tips ...

Page 55: ...dule v1 02a www xilinx com 55 PG052 October 16 2012 Appendix C Application Software Development Device Drivers The I O Module is supported by the IO Module driver included with Xilinx Software Development Kit ...

Page 56: ...nfiguration User Guide UG470 3 Vivado Design Suite Migration Methodology Guide UG911 Technical Support Xilinx provides technical support at www xilinx com support for this LogiCORE IP product when used as described in the product documentation Xilinx cannot guarantee timing functionality or support of product if implemented in devices that are not defined in the documentation if customized beyond ...

Page 57: ...ably foreseeable or Xilinx had been advised of the possibility of the same Xilinx assumes no obligation to correct any errors contained in the Materials or to notify you of updates to the Materials or to product specifications You may not reproduce modify distribute or publicly display the Materials without prior written consent Certain products are subject to the terms and conditions of the Limit...

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