10GBASE-KR Ethernet TRD
8
UG1058 (v2017.1) April 19, 2017
Chapter 1:
Introduction
• Ethernet Controller application GUI/Driver:
°
Provides a graphical user interface running on the control computer to pass user
inputs to the 10GBASE-KR TRD and to display status through the KCU1250 board
USB-to-UART port.
• Eye scan system:
°
AXI DRP bridge:
- Custom logic that allows access to DRP registers of the transceiver through any
AXI master such as the MicroBlaze processor subsystem.
°
AXI block RAM controller:
- An AXI slave IP core that allows access to local block RAM by AXI master devices
such as the MicroBlaze processor subsystem and the JTAG to AXI Master IP core.
- The block RAM stores the data read from the DRP port of the transceiver.
°
JTAG to AXI Master:
- An AXI Master IP core that can generate AXI transactions and drive AXI signals
internal to FPGA in the system.
- Communicates with the AXI block RAM controller via the AXI Interconnect.
- Allows the Vivado® tools logic analyzer Tcl console running on the control
computer to interact with FPGA through the USB-to-JTAG port on the KCU1250
board.
°
MicroBlaze processor subsystem:
- An AXI Master that communicates with the AXI DRP bridge and AXI block RAM
controller via the AXI Interconnect.
- Drivers running on the MicroBlaze processor subsystem implement an algorithm
to measure a statistical eye (bit error ratio (BER) versus time and voltage offset).
Data sampling points are available to read via the DRP port of the transceiver.
Point-by-point measured data is stored in a block RAM to be burst read by the
control computer via the JTAG to AXI Master.
°
AXI Interconnect:
- Allows multiple AXI masters (MicroBlaze processor subsystem and JTAG to AXI
Master) to communicate with multiple AXI slaves (AXI DRP Bridge and AXI block
RAM controller).
