10GBASE-KR Ethernet TRD
46
UG1058 (v2017.1) April 19, 2017
Chapter 4:
Implementing and Simulating the Design
eyescan_sys.bd
contains the JTAG to AXI Master IP core, AXI BRAM Controller IP
core, DRP to AXI bridge logic, and the MicroBlaze processor subsystem.
The design top level file
kcu1250_10gbasekr_top.v
instantiates the block designs
The top level file also instantiates the VIO cores to configure and monitor the
10-Gigabit Ethernet PCS/PMA IP core.
3. In the Flow Navigator, click
Generate Bitstream
.
4. In the No Implementation Results Available window, click
Yes
. The bitstream will be
generated and available at:
<working_dir>/kcu1250_10gbasekr_trd/hardware/vivado/runs/impl_run/
10gbasekr_trd.runs/impl_1/kcu1250_10gbasekr_top.bit
.
NOTE:
It takes about an hour to build the bitstream.
X-Ref Target - Figure 4-2
Figure 4-2:
Vivado Project, Sources View
X18463-120716
