10GBASE-KR Ethernet TRD
67
UG1058 (v2017.1) April 19, 2017
Chapter 5:
Reference Design Details
The data flow with internal generator mode enabled on the Traffic Generator for channel 0
is:
Generator module CH0
→
CH0 TX AXI4-Stream interface of the 10-Gigabit Ethernet
MAC IP
→
CH0 TX XGMII interface of the 10-Gigabit Ethernet PCS/PMA IP
→
CH0
TXN/TXP serial lines
→
loopback to CH1 RXN/RXP serial lines
→
CH1 RX XGMII
interface of the 10-Gigabit Ethernet PCS/PMA
→
CH1 RX AXI4-Stream interface of the
10-Gigabit Ethernet MAC IP core
The data flow with internal generator mode enabled on Traffic Generator for channel 1 is:
Generator module CH1
→
CH1 TX AXI4-Stream interface of the 10-Gigabit Ethernet
MAC IP
→
CH1 TX XGMII interface of the 10-Gigabit Ethernet PCS/PMA IP
→
CH1
TXN/TXP serial lines
→
loopback to CH0 RXN/RXP serial lines
→
CH0 RX XGMII
interface of the 10-Gigabit Ethernet PCS/PMA IP
→
CH0 RX AXI4-Stream interface of the
10-Gigabit Ethernet MAC IP core
Ethernet Performance Monitor
The Ethernet performance monitor block snoops for valid transactions on the AXI4-Stream
interface ports of the 10-Gigabit Ethernet MAC IP core and keeps track of bandwidth
utilization. A timer within this block counts the clocks until one second has elapsed, during
which time counters have collected data about link performance.
Four counters collect information on the transactions on the AXI4-Stream interface:
• TX Payload Byte Count. This counter counts bytes transferred when tx_tvalid and
tx_tready signals are asserted between the Traffic Generator block and the 10G MAC. At
the end of the packet (tx_tlast) 14 bytes of header are subtracted from the count to get
payload count.
• TX Packet Count. This counter counts the number of transmitted packets. The counter
increments when tx_tvalid and tx_tready and tx_tlast signal are asserted.
• RX Payload Byte Count. This counter counts bytes transferred when rx_tvalid and
rx_tready signals are asserted between the Traffic Generator block and the 10G MAC. At
tx_axis_tuser
Output
If asserted indicates an underrun frame. This is tied to
1'b0
.
tx_axis_tready
Input
Destination ready for transmit. Indicates that the 10-Gigabit Ethernet
MAC IP core is ready to accept data on tx_axis_tdata.
The simultaneous assertion of tx_axis_tvalid and tx_axis_tready marks the
successful transfer of one data beat on tx_axis_tdata.
Control Ports
enable_gen
Input
Enable internal generator.
data_payload
Input
Size of the payload (46 bytes to 1,500 Bytes).
Table 5-2:
Generator Module Parameters and Ports
(Cont’d)
Port/Parameter Name
Type
Description
