Chapter 1
IP Facts
The Xilinx
®
LogiCORE™ IP I2S Transmitter and LogiCORE™ Receiver cores are soft Xilinx IP cores
for use with the Xilinx Vivado
®
Design Suite, which makes it easy to implement inter-IC-sound
(I2S) interface used to connect audio devices for transmitting and receiving PCM audio.
Features
• AXI4-Stream compliant
• Supports up to four I2S channels (upto eight Audio channels)
• 16/24 bit data
• Supports Master I2S mode
• Configurable FIFO depth
• Supports the AES channel status extraction/insertion
IP Facts
LogiCORE IP Facts Table
Core Specifics
Supported Device Family
1
Ult™, UltraScale™, Zynq
®
-7000 SoC, 7 series, Zynq
®
Ult™ MPSoC.
Supported User Interfaces
AXI4-Lite, AXI4-Stream, AXI4
Resources
Performance and Resource Use web page
for transmitter
and
Performance and Resource Use web page
for receiver.
Provided with Core
Design Files
System Verilog
Example Design
System Verilog
Test Bench
System Verilog
Constraints File
Delivered at the time of IP generation
Simulation Model
Source HDL
Supported S/W Driver
2
Standalone
Chapter 1: IP Facts
PG308 (v1.0) April 4, 2018
www.xilinx.com
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I2S Transmitter and I2S Receiver
4
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