Table 14: Register Address Space (cont'd)
Address (hex)
Register Name
0x34
Channel 2/3 Control: Channel 2/3 control register
0x38
Channel 4/5 Control: Channel 4/5 control register
0x3C
Channel 6/7 Control: Channel 6/7 control register
0x50
AES Channel Status 0: Register to specify the LSB 32 bit of
the AES Channel Status
0x54
AES Channel Status 1: Register to specify the next LSB 32 bit
of the AES Channel Status
0x58
AES Channel Status 2: Register to specify the 32 bit of the
AES Channel Status
0x5C
AES Channel Status 3: Register to specify the 32 bit of the
AES Channel Status
0x60
AES Channel Status 4: Register to specify the 32 bit of the
AES Channel Status
0x64
AES Channel Status 5: Register to specify the MSB 32 bit of
the AES Channel Status
Core Version (0x00)
This register returns the major and minor versions of the IP core.
Table 15: Receiver Core Version (0x00)
Bit
Default
Value
Access
Type
Description
31:16
0x1
RO
Major Revision: This is the IP major revision value. For example if the IP version is
1.2, then this will return a value of 1.
15:0
0x0
RO
Minor Revision: This is the IP minor revision value. For example if the IP version
is 1.2, then this will return a value of 2.
Core Configuration (0x04)
This register returns the IP Configuration.
Table 16: Receiver Core Configuration (0x04)
Bit
Default
Value
Access
Type
Description
31:17
RSVD
16
RO
I2S Data Width: Indicates the I2S Data width of the core
1 = 24 bit
0 = 16 bit
15:12
RSVD
11:8
RO
Number of Audio Channels: Indicates the number of audio channels supported.
Valid values are 2, 4, 6 and 8
Chapter 3: Product Specification
PG308 (v1.0) April 4, 2018
www.xilinx.com
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I2S Transmitter and I2S Receiver
17
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