Clock Placement
Audio Clock, if supplied from an external source, should be connected to a clock capable IO so
that it can be used by FPGA fabric.
Banking
This section is not applicable for this IP core.
Transceiver Placement
This section is not applicable for this IP core.
I/O Standard and Placement
This section is not applicable for this IP core.
Simulation
For comprehensive information about Vivado
®
simulation components, as well as information
about using supported third-party tools, see the Vivado Design Suite User Guide: Logic Simulation
(
UG900
).
Synthesis and Implementation
For details about synthesis and implementation, see the Vivado Design Suite User Guide: Designing
with IP (
UG896
).
Chapter 5: Design Flow Steps
PG308 (v1.0) April 4, 2018
www.xilinx.com
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I2S Transmitter and I2S Receiver
31
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