XESS XStend, Manual

Page: 9 / 34

Table 2: Jumper settings for XStend RAMs.
Jumper Setting
J16 Removing the shunt on this jumper disables the left
RAM U5 by pulling its chip-select pin high.
J17 Removing the shunt on this jumper disables the right
RAM U6 by pulling its chip-select pin high.
Here are the connections from the XS40 and XS95 Boards to their own RAMs and the RAMs of
the XStend Board (expressed as UCF constraints):
Listing 9: Connections between the XStend RAMs and the XS40.
NET AD0 LOC=P41; # DATA BUS
NET AD1 LOC=P40;
NET AD2 LOC=P39;
NET AD3 LOC=P38;
NET AD4 LOC=P35;
NET AD5 LOC=P81;
NET AD6 LOC=P80;
NET AD7 LOC=P10;
NET A0 LOC=P3; # LOWER BYTE OF ADDRESS
NET A1 LOC=P4;
NET A2 LOC=P5;
NET A3 LOC=P78;
NET A4 LOC=P79;
NET A5 LOC=P82;
NET A6 LOC=P83;
NET A7 LOC=P84;
NET A8 LOC=P59; # UPPER BYTE OF ADDRESS
NET A9 LOC=P57;
NET A10 LOC=P51;
NET A11 LOC=P56;
NET A12 LOC=P50;
NET A13 LOC=P58;
NET A14 LOC=P60;
NET A15 LOC=P28;
NET WR_ LOC=P62; # ACTIVE-LOW WRITE-ENABLE FOR ALL RAMS
NET OE_ LOC=P61; # ACTIVE-LOW OUTPUT-ENABLE FOR ALL RAMS
NET CE_ LOC=P65; # ACTIVE-LOW CHIP-ENABLE FOR XS40 RAM
NET LCE_ LOC=P7; # ACTIVE-LOW CHIP-ENABLE FOR LEFT XSTEND RAM
NET RCE_ LOC=P8; # ACTIVE-LOW CHIP-ENABLE FOR RIGHT XSTEND RAM
Listing 10: Connections between the XStend RAMs and the XS95.
NET AD0 LOC=P44; # DATA BUS
NET AD1 LOC=P43;
NET AD2 LOC=P41;
NET AD3 LOC=P40;
NET AD4 LOC=P39;
NET AD5 LOC=P37;