XESS XStend, Manual

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070- "4-bit pixels so make a new RAM address every two dot clks and ignore
071- "hcnt0 when addressing the RAM. Also repeat each line of pixels twice
072- "(so the pixels are approximately square on the screen), so ignore vcnt0
073- "when addressing the RAM.
074- vram_addr = [vcnt8..vcnt1,hcnt7..hcnt1];
075-
076- pixrg.ACLR = !push_reset_;
"clear pixel register on reset
077- pixrg.CLK = clk; "pixel clk controls changes in pixel register
078- "the pixel reg is loaded with from the RAM when the lower bit of the
079- "horizontal counter is zero. The active pixel is in the lower four
080- "bits of the pixel reg. On the next clk, the pixel reg is left-shifted
081- "by four bits to bring the other pixel into the active position.
082- WHEN (hcnt0==0)
083- THEN pixrg := vram_data
"load 2 pixels from RAM
084- ELSE pixrg := [0,0,0,0,pixrg7..pixrg4]; "left-shift pixel reg four bits
085-
086- "delay the video blanking by one clk to account for RAM access delay
087- delayed_blank.ACLR = !push_reset_;
088- delayed_blank.CLK = clk;
089- delayed_blank := video_blank;
090-
091- "color mapper that translates each 4-bit pixel into a 6-bit RGB value.
092- "when the video signal is blanked, the RGB value is forced to 0.
093- rgb.ACLR = !push_reset_;
094- rgb.CLK = clk;
095- TRUTH_TABLE ([delayed_blank, pixel] :> rgb)
096- [ 0 ,^b0000 ] :> ^b000000; "black
097- [ 0 ,^b0001 ] :> ^b101010; "light-gray
098- [ 0 ,^b0010 ] :> ^b111111; "white
099- [ 0 ,^b0011 ] :> ^b110000; "red
100- [ 0 ,^b0100 ] :> ^b001100; "green
101- [ 0 ,^b0101 ] :> ^b000011; "blue
102- [ 0 ,^b0110 ] :> ^b111100; "yellow
103- [ 0 ,^b0111 ] :> ^b110011; "magenta
104- [ 0 ,^b1000 ] :> ^b001111; "cyan
105- [ 0 ,^b1001 ] :> ^b100000; "dark-red
106- [ 0 ,^b1010 ] :> ^b001000; "dark-green
107- [ 0 ,^b1011 ] :> ^b000010; "dark-blue
108- [ 0 ,^b1100 ] :> ^b101000; "tan
109- [ 0 ,^b1101 ] :> ^b100010; "purple
110- [ 0 ,^b1110 ] :> ^b001010; "teal
111- [ 0 ,^b1111 ] :> ^b010101; "dark-gray
112- [ 1 ,X ] :> ^b000000; "black during blanking
113-
114- END VGACORE
Listing 17: UCF file for VGA XStend example with XS40.
001- # CLOCK FROM XS40 OSCILLATOR
002- NET CLK
LOC=P13;
003- #
004- # MICROCONTROLLER PINS
005- NET RST
LOC=P36; # ACTIVE-HIGH RESET
006- NET WR_ LOC=P62; # ACTIVE-LOW WRITE (ALSO CONTROLS RAM)
007- NET AD0 LOC=P41; # MULTIPLEXED ADDRESS/DATA BUS
008- NET AD1 LOC=P40;
009- NET AD2 LOC=P39;
010- NET AD3 LOC=P38;
011- NET AD4 LOC=P35;