XESS XStend, Manual

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Table 4: Connections between the XS40 Board and XStend Board resources.
XS40 Bus (J1,J3,J18) XS95 Pins (J2) Power/ GND DIP Switch Push-buttons LEDs VGA Interface PS/2 Interface RAMs Stereo Codec 8051 Uc PC Parallel Port Oscillator
Function
UW-FPGA BOARD Pin
1 77 Uncommitted XS95 I/O pin
2 78 +5V +5V power source
3 1 LS_0 A0 LED segment; address line P35
4 2 LS_1 A1 LED segment; address line P36
5 3 LS_2 A2 LED segment; address line P29
6 5 DIPSW4 LRCK P13 DIP switch; codec control; uC I/O P24
7 6 DIPSW1 LCE_ P10 DIP switch; RAM chip-enable, uC I/O port P19
8 7 DIPSW2 RCE_ P11 DIP switch; RAM chip-enable, uC I/O port P20
9 11 DIPSW3 MCLK P12 DIP switch; codec clock; uC I/O port P23
10 35 D_8 AD7 P07 LED; RAM data line; uC muxed address/data line P61
11 31 Uncommitted XS95 I/O pin
12 69 Uncommitted XS95 I/O pin
13 9 CLK XS40/95 oscillator output
14 13 PSEN_ uC program storage-enable
15 28 JTAG TDI; DIN
16 30 JTAG TCK; CCLK
17 29 JTAG TMS
18 14 S5 RED1 XS Board LED segment; VGA color signal
19 15 S6 HSYNC_ XS Board LED segment; VGA horiz. sync.
20 17 S3 GREEN1 XS Board LED segment; VGA color signal
21 68 Uncommitted XS95 I/O pin
22 33 Uncommitted XS95 I/O pin
23 18 S4 RED0 XS Board LED segment; VGA color signal
24 19 S2 GREEN0 XS Board LED segment; VGA color signal
25 21 S0 BLUE0 XS Board LED segment; VGA color signal
26 23 S1 BLUE1 XS Board LED segment; VGA color signal
27 32 RD_ uC read line
28 34 RDP_ A15 P27 LED decimal-point; address line; uC I/O port P41
29 20 ALE_ uC address-latch-enable
30 Serial EEPROM chip-enable
31 12 Uncommitted XS95 I/O pin
32 81 PC_D6 PC parallel port output
33 25 Uncommitted XS95 I/O pin
34 80 PC_D7 PC parallel port output
35 39 D_5 AD4 P04 LED; RAM data line; uC muxed address/data line P66
36 45 RST uC reset line
37 10 RESET_ XTAL1 Pushbutton; uC clock line P56
38 40 D_4 AD3 P03 LED; RAM data line; uC muxed address/data line P57
39 41 D_3 AD2 P02 LED; RAM data line; uC muxed address/data line P58
40 43 D_2 AD1 P01 LED; RAM data line; uC muxed address/data line P59
41 44 D_1 AD0 P00 LED; RAM data line; uC muxed address/data line P60
42 4 Uncommitted XS95 I/O pin
43 Unconnected
44 46 CCLK PC_D0 Codec control line; PC parallel port output
45 47 CDIN PC_D1 Codec control line; PC parallel port output
46 48 CS_ PC_D2 Codec control line; PC parallel port output
47 50 PC_D3 PC parallel port output
48 51 PC_D4 PC parallel port output
49 52 PC_D5 PC parallel port output
50 53 RS_4 A12 P24 LED segment; address line; uC I/O port P48
51 54 RS_2 A10 P22 LED segment; address line; uC I/O port P45
52 49 GND Power supply ground
53 Unconnected
54 +3.3V +3.3V/+5V power supply (4000E/4000XL)
55 PROGRAM XS40 configuration control P55
56 55 RS_3 A11 P23 LED segment; address line; uC I/O port P51
57 56 RS_1 A9 P21 LED segment; address line; uC I/O port P47
58 57 RS_5 A13 P25 LED segment; address line; uC I/O port P50
59 58 RS_0 A8 P20 LED segment; address line; uC I/O port P46
60 61 RS_6 A14 P26 LED segment; address line; uC I/O port P49
61 62 OE_ RAM output-enable
62 63 WR_ P36 RAM write-enable; uC I/O port
63 Unconnected
64 Unconnected
65 65 CE_ XS Board RAM chip-enable
66 66 DIPSW7 SDOUT P16 DIP switch; codec output data; uC I/O port P27
67 24,67 SPARE_ VSYNC_ P17 Pushbutton; VGA horiz. sync.; uC I/O port P18
68 26 KB_CLK P34 PS/2 keyboard clock; uC I/O port
69 70 DIPSW8 KB_DATA P31 DIP switch; keyboard serial data; uC I/O port P28
70 71 DIPSW6 SDIN P15 DIP switch; codec input data; uC I/O port P26
71 28 JTAG TDI; DIN
72 59 JTAG TDO; DOUT
73 30 JTAG TCK; CCLK
74 74 Uncommitted XS95 I/O pin
75 59 JTAG TDO; DOUT
76 76 Uncommitted XS95 I/O pin
77 72 DIPSW5 SCLK P14 DIP switch; codec serial clock; uC I/O port P25
78 75 LS_3 A3 LED segment; address line P44
79 79 LS_4 A4 LED segment; address line P38
80 36 D_7 AD6 P06 LED; RAM data line; uC muxed address/data line P62
81 37 D_6 AD5 P05 LED; RAM data line; uC muxed address/data line P65
82 82 LS_5 A5 LED segment; address line P40
83 83 LS_6 A6 LED segment; address line P39
84 84 LDP_ A7 LED decimal-point; address line P37