Hardware Reference Guide
SST-PFB3-ISA
28
Hardware
Register
Details
©2004 Woodhead Software & Electronics, Division of Woodhead Canada Limited
Document Edition: 1.0, Document #: 715-0078, Template Edition: 1.1, Template #: QMS-06-045
Use, duplication or disclosure of this document or any of the information contained herein is subject to the restrictions on page ii of this document.
Bit Name
Description
HostIrq0
•
This bit is used by the card’s processor to send interrupts to interrupt flag 0 of the host.
•
Writing 1 acknowledges the interrupt and clears it
•
Writing 0 has no effect
•
Reading 1 indicates interrupt in progress
•
Reading 0 indicates interrupt complete
CardIrq1
This bit is used by the host to send interrupts to interrupt flag 1 of the card’s processor.
•
Writing 1 generates an interrupt
•
Writing 0 has no effect
•
Reading 1 indicates interrupt in progress
•
Reading 0 indicates interrupt complete
CardIrq0
This bit is used by the host to send interrupts to interrupt flag 0 of the card’s processor.
•
Writing 1 generates an interrupt
•
Writing 0 has no effect
•
Reading 1 indicates interrupt in progress
•
Reading 0 indicates interrupt complete
3.1.3 AddrMatch Register
This register controls the card’s base memory address in host memory space.
Table 10: AddrMatch Register Settings
Bit
7
6
5
4
3
2
1
0
Name
AM19 AM18 AM17 AM16 AM15 AM14 AM13 AM12
Read/Write
R R/W R/W R/W R/W R/W R/W R
Reset
1 0 0 0 0 0 0 0
Table 11: AddrMatch Register Values
Bit and Value
Hex
Address
AM19 AM18 AM17 AM16 AM15 AM14 AM13 AM12
1 0 0 0 0 0 0 0 0x80 0x80000
1 0 0 0 0 0 1 0 0x82 0x82000
1 0 0 0 0 1 0 0 0x84 0x84000
1 0 0 0 0 1 1 0 0x86 0x86000
1 0 0 0 1 0 0 0 0x88 0x88000
1 0 0 0 1 0 1 0 0x8A
0x8A000
1 0 0 0 1 1 0 0 0x8C
0x8C000
1 0 0 0 1 1 1 0 0x8E
0x8E000
1 0 0 1 0 0 0 0 0x90 0x90000
1 0 0 1 0 0 1 0 0x92 0x92000