WM9090
Production Data
w
PD, November 2010, Rev 4.1
70
REGISTER
ADDRESS
BIT LABEL
DEFAULT
DESCRIPTION
REFER
TO
5:4 DCS_DAC_W
R_COMPLETE
[1:0]
00
DC Servo DAC Write status
0 = DAC Write DC Servo mode not completed.
1 = DAC Write DC Servo mode complete.
Bit [1] = HPOUT1R
Bit [0] = HPOUT1L
1:0 DCS_STARTU
P_COMPLETE
[1:0]
00
DC Servo Start-Up status
0 = Start-Up DC Servo mode not completed.
1 = Start-Up DC Servo mode complete.
Bit [1] = HPOUT1R
Bit [0] = HPOUT1L
Register 58h
DC Servo Readback 0
REGISTER
ADDRESS
BIT LABEL
DEFAULT
DESCRIPTION
REFER
TO
R89 (59h)
DC Servo
Readback 1
7:0 DCS_DAC_W
R_VAL_1_RD
[7:0]
0000_0000 Readback value for HPOUT1R.
Two’s complement format.
LSB is 0.25mV.
Range is -32mV to +31.75mV
Register 59h
DC Servo Readback 1
REGISTER
ADDRESS
BIT LABEL
DEFAULT
DESCRIPTION
REFER
TO
R90 (5Ah)
DC Servo
Readback 2
7:0 DCS_DAC_W
R_VAL_0_RD
[7:0]
0000_0000 Readback value for HPOUT1L.
Two’s complement format.
LSB is 0.25mV.
Range is -32mV to +31.75mV
Register 5Ah
DC Servo Readback 2
REGISTER
ADDRESS
BIT LABEL
DEFAULT
DESCRIPTION
REFER
TO
R96 (60h)
Analogue
HP 0
7 HPOUT1L_RM
V_SHORT
0
Removes HPOUT1L short
0 = HPOUT1L short enabled
1 = HPOUT1L short removed
For pop-free operation, this bit should be set to 1 as the
final step in the HPOUTL Enable sequence.
6 HPOUT1L_OU
TP
0
Enables HPOUT1L output stage
0 = Disabled
1 = Enabled
For pop-free operation, this bit should be set to 1 after
the DC offset cancellation has been performed.
5 HPOUT1L_DL
Y
0
Enables HPOUT1L intermediate stage
0 = Disabled
1 = Enabled
For pop-free operation, this bit should be set to 1 after
the output signal path has been configured, and before
the DC Offset cancellation is scheduled This bit should
be set with at least 20us delay after HPOUT1L_ENA.
