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WM9090

Production Data

PD, November 2010, Rev 4.1

Secondly, initiate the sequence by performing the following set of register writes.

REGISTER

ADDRESS

DATA DESCRIPTION

R1 (01h)
Power Management (1)

0x000B OSC_ENA=1,

VMID_RES=01,

BIAS_ENA=1

R2 (02h)
Power Management (2)

0x60C0 Enable

input

PGAs

R22 (16h)
IN1 Line Control

0x0000

IN1+/- to s/e mode and disable input
clamp

R24 (18h)
IN1 Line Input A Volume

0x0100

IN1A Volume=-6dB and update

R25 (19h)
IN1 Line Input B Volume

0x0100

IN1B Volume=-6dB and update

R70 (46h)
Write Sequencer 0

0x0100

Write Sequencer enable

R71 (47h)
Write Sequencer 0

0x0100 WSEQ_START=1

Summary of Contents for WM9090

Page 1: ...led using a two wire I2C interface An integrated oscillator generates all internal clocks removing the need to provide any external clock WM9090 is available in a 2 53mm x 2 07mm 20 bump CSP package F...

Page 2: ...ENABLE 16 INPUT PGA CONFIGURATION 17 INPUT PGA VOLUME CONTROL 17 OUTPUT SIGNAL PATH 20 OUTPUT SIGNAL PATHS ENABLE 20 SPEAKER MIXER CONTROL 21 SPEAKER OUTPUT VOLUME CONTROL 22 SPEAKER BOOST MIXER CONTR...

Page 3: ...OWER MANAGEMENT 53 THERMAL SHUTDOWN 55 SOFTWARE RESET AND CHIP ID 55 REGISTER MAP 56 REGISTER BITS BY ADDRESS 58 APPLICATIONS INFORMATION 74 RECOMMENDED EXTERNAL COMPONENTS 74 AUDIO INPUT PATHS 75 POW...

Page 4: ...IN CONFIGURATION 20 bump CSP package Top View ORDERING INFORMATION ORDER CODE TEMPERATURE RANGE PACKAGE MOISTURE SENSITIVITY LEVEL PEAK SOLDERING TEMPERATURE WM9090ECS R 40 C to 85 C 20 ball W CSP Pb...

Page 5: ...4 IN1N Analogue Input IN1 negative analogue input B5 IN1P Analogue Input IN1 positive analogue input C1 CPVOUTP Analogue Output Charge pump positive rail decoupling pin C2 AVDD Supply Analogue supply...

Page 6: ...age conditions prior to surface mount assembly These levels are MSL1 unlimited floor life at 30 C 85 Relative Humidity Not normally stored in moisture barrier bag MSL2 out of bag storage for 1 year at...

Page 7: ...7 dB Maximum Programmable Gain 6 dB Programmable Gain Step Size 1 dB Mute Attenuation HPOUT1LVOL and HPOUT1RVOL 75 dB SPKVOL 66 dB Speaker Output Programmable Gain SPKOUTLBOOST Programmable Gain SPKOU...

Page 8: ...3 7V THD N 1 Speaker Boost 12dB 750 mW Quiescent Current 3 mA Leakage Currents SVDD Leakage Current 0 2 A HPVDD Leakage Current VMID_ENA 0 VMID_BUF_ENA 0 and TSHUT_ENA 0 1 A Analogue Reference Level...

Page 9: ...and right to left channel crosstalk is the measured signal level in the idle channel at the test signal frequency relative to the signal level at the output of the active channel The active channel is...

Page 10: ...WM9090 Production Data w PD November 2010 Rev 4 1 10 PERFORMANCE PLOTS...

Page 11: ...0 2 2 4 3 SPKKVDD LDO1VDD iSPKVDD iLDO1VDD Total Power V V mA mA mW IN1 IN1 Stereo to Headphone 16ohm load 3 6 1 8 0 00 3 36 6 0 IN2 IN2 Differential to Speaker Class D 8ohm 10 H 6dB boost 3 6 1 8 2 5...

Page 12: ...MIX IN1A_SPKMIX_VOL IN1B_TO_SPKMIX IN1B_SPKMIX_VOL IN2A_TO_SPKMIX IN2A_SPKMIX_VOL IN2B_TO_SPKMIX IN2B_SPKMIX_VOL IN1A_TO_MIXOUTL IN1A_MIXOUTL_VOL IN2A_TO_MIXOUTL IN2A_MIXOUTL_VOL SPKLVOL_ENA SPKMIX_MU...

Page 13: ...GA gain 0dB unless otherwise stated PARAMETER SYMBOL MIN TYP MAX UNIT SCLK Frequency 400 kHz SCLK Low Pulse Width t1 1300 ns SCLK High Pulse Width t2 600 ns Hold Time Start Condition t3 600 ns Setup T...

Page 14: ...ponse and enables direct headphone connection without any DC blocking capacitors A DC Servo circuit is provided for DC offset measurement and correction thereby suppressing pops and reducing power con...

Page 15: ...of combinations Up to two differential line inputs to analogue mixers Up to four single ended line inputs to analogue mixers The inputs may be mixed together or independently routed to different comb...

Page 16: ...input pins are clamped to VMID in order to prevent audible pops caused by enabling the input paths When one or more analogue input path is in use the respective input clamp s must be disabled using t...

Page 17: ...1A IN2A input PGAs have a controlled gain range of 0dB to 24dB In differential mode these PGAs have a controlled gain range of 6dB to 18dB To prevent zipper noise a zero cross function is provided on...

Page 18: ...IN1B input PGA volumes to be updated simultaneously 7 IN1B_MUTE 1 IN1B PGA Mute 0 Un Mute 1 Mute 6 IN1B_ZC 0 IN1B PGA Zero Cross Control 0 Change gain immediately 1 Change gain on zero cross only 2 0...

Page 19: ...B 101 18dB 110 24dB 111 24dB R27 1Bh IN2 Line Input B Volume 8 IN2_VU N A Input PGA Volume Update Writing a 1 to this bit will cause IN2A and IN2B input PGA volumes to be updated simultaneously 7 IN2B...

Page 20: ...re 3 Control Registers for Output Signal Path OUTPUT SIGNAL PATHS ENABLE The output mixers and drivers can be independently enabled and disabled as described in Table 4 See Power Sequences and Pop Sup...

Page 21: ...ping The gain of each input path is adjustable using a selectable volume control in each path to facilitate this The Speaker Mixer output can be muted or enabled using the SPKMIX_MUTE register bit The...

Page 22: ...lume Update Writing a 1 to this bit will update the SPKOUTL volume 7 SPKOUTL_ZC 0 Speaker Output PGA Zero Cross Control 0 Change gain immediately 1 Change gain on zero cross only 6 SPKOUTL_MUTE 0 Spea...

Page 23: ...adphone Output PGAs as defined in Table 10 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R45 2Dh Output Mixer1 6 IN1A_TO_MIXOUTL 0 IN1A to MIXOUTL enable 0 Disabled 1 Enabled 2 IN2A_TO_MIXOUTL 0 IN2A...

Page 24: ...PGA volume settings are both updated when a 1 is written to either HPOUT1_VU bit This makes it possible to update the gain of the left and right output paths simultaneously A zero cross function is p...

Page 25: ...UT1L_VOL 5 0 2Dh 12dB Left Headphone Output PGA Volume 57dB to 6dB in 1dB steps See Table 11 for output PGA volume control range R29 1Dh Right Output Volume 8 HPOUT1_VU N A Headphone Output PGA Volume...

Page 26: ...25h 20 6h 51 26h 19 7h 50 27h 18 8h 49 28h 17 9h 48 29h 16 Ah 47 2Ah 15 Bh 46 2Bh 14 Ch 45 2Ch 13 Dh 44 2Dh 12 Eh 43 2Eh 11 Fh 42 2Fh 10 10h 41 30h 9 11h 40 31h 8 12h 39 32h 7 13h 38 33h 6 14h 37 34h...

Page 27: ...will result in a more gradual gain adjustment but the AGC may also be slower to remove signal clipping under this selection Note that the AGC attenuation has a step size of 0 5dB providing a high reso...

Page 28: ...98 62h AGC Control 0 15 AGC_CLIP_ENA 1 Enable AGC Anti Clip Mode 0 Disabled 1 Enabled 11 8 AGC_CLIP_THR 3 0 0110 AGC Anti Clip Threshold Sets the headroom between SPKPGA output and SPKVDD at which Ant...

Page 29: ...GC_PWR_AVG 1 then the AGC responds to the RMS power level as quoted above When AGC_PWR_AVG 0 then the AGC responds to the instantaneous voltage at the speaker output Selecting the RMS power level is r...

Page 30: ...450mW 0100 500mW 0101 550mW 0110 600mW 0111 650mW 1000 700mW 1001 750mW 1010 800mW 1011 850mW 1100 900mW 1101 950mW 1110 1000mW 1111 1050mW 6 4 AGC_PWR_ATK 2 0 000 AGC Power Limiting Attack Rate Sets...

Page 31: ...op noise the SPKOUTL_BOOST register should not be modified while the speaker output is enabled Figure 4 illustrates the speaker output and the mixing and gain boost options available Ultra low leakage...

Page 32: ...dio band under certain conditions Possible sources of these instabilities include the inductive load of a headphone coil or an active load in the form of an external line amplifier The capacitance of...

Page 33: ...BIT LABEL DEFAULT DESCRIPTION R1 01h Power Management 1 3 OSC_ENA 0 CLK_SYS Oscillator Enable 0 Disabled 1 Enabled R6 06h Clocking 1 15 TOCLK_RATE 0 TOCLK Rate Divider 2 0 f 2 1 f 1 14 TOCLK_ENA 0 TO...

Page 34: ...The controller indicates the start of data transfer with a high to low transition on SDA while SCLK remains high This indicates that a device ID register address and data will follow The WM9090 respon...

Page 35: ...TART Figure 8 Control Interface Register Read The Control Interface also supports other register operations as listed above The interface protocol for these operations is summarised below The terminol...

Page 36: ...fied Address Figure 10 Single Register Read from Specified Address Figure 11 Multiple Register Write to Specified Address using Auto increment Figure 12 Multiple Register Read from Specified Address u...

Page 37: ...c steps within the sequence Note that the Control Write Sequencer s internal clock is derived from the internal clock CLK_SYS which must be enabled by setting OSC_ENA see Clocking Control The clock di...

Page 38: ...ontrol Initiating a Sequence PROGRAMMING A SEQUENCE A sequence consists of write operations to data bits or groups of bits within the control registers The Register fields associated with programming...

Page 39: ...range of execution delay times from 562 s up to 2 048s per step WSEQ_EOS is a 1 bit field which indicates the End of Sequence If this bit is set then the Control Write Sequencer will automatically st...

Page 40: ...bit 01 WSEQ_DATA_START 0001b and the Data width is 2 bits WSEQ_DATA_WIDTH 0001b With these settings the Control Write Sequencer would update the Control Register R1 2 1 with the contents of WSEQ_DATA...

Page 41: ...rol Write Sequencer at Index Address 0 00h and executes the sequence defined in Table 21 This sequence takes approximately 40ms to run WSEQ INDEX REGISTER ADDRESS WIDTH START DATA DELAY EOS DESCRIPTIO...

Page 42: ...DEX REGISTER ADDRESS WIDTH START DATA DELAY EOS DESCRIPTION 16 10h R96 60h 7 bits Bit 1 00h 0h 0b HPOUT1R_DLY 0 HPOUT1R_OUTP 0 HPOUT1R_RMV_SHORT 0 HPOUT1L_DLY 0 HPOUT1L_OUTP 0 HPOUT1L_RMV_SHORT 0 dela...

Page 43: ...its defined in Table 23 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R22 16h IN1 Line Control 0 IN1_CLAMP 1 IN1P and IN1N input pad VMID clamp 0 Clamp de activated 1 Clamp activated R23 17h IN2 Line...

Page 44: ...as the first stage of the HPOUTR Enable sequence R96 60h Analogue HP 0 7 HPOUT1L_RMV_ SHORT 0 Removes HPOUT1L short 0 HPOUT1L short enabled 1 HPOUT1L short removed For pop free operation this bit sho...

Page 45: ...e following sequence into the Control Write Sequencer For further details refer to the Programming a Sequence section WSEQ INDEX REGISTER ADDRESS WIDTH START DATA DELAY EOS DESCRIPTION 0 00h R76 4Ch 1...

Page 46: ...x000B OSC_ENA 1 VMID_RES 01 BIAS_ENA 1 R2 02h Power Management 2 0x60C0 Enable input PGAs R22 16h IN1 Line Control 0x0000 IN1 to s e mode and disable input clamp R24 18h IN1 Line Input A Volume 0x0100...

Page 47: ...uency in order to optimise the power consumption according to the operating conditions The Charge Pump mode of operation is selected automatically according to the HPOUT1L_VOL and HPOUT1R_VOL register...

Page 48: ...and periodically recurring events Writing a logic 1 to DCS_TRIG_STARTUP_n initiates a series of DC offset measurements and applies the necessary correction to the associated output n 0 for Left chann...

Page 49: ...r HPOUT1L In readback a value of 1 indicates that the DC Servo DAC Write correction is in progress 1 DCS_ENA_CHAN_1 0 DC Servo enable for HPOUT1R 0 Disabled 1 Enabled 0 DCS_ENA_CHAN_0 0 DC Servo enabl...

Page 50: ...st the DC offset correction on the selected channel by no more than 1LSB 0 25mV Setting DCS_TIMER_PERIOD_01 to a non zero value will cause a single DC offset measurement and adjustment to be scheduled...

Page 51: ...PERIOD 0000 Off 0001 0 52s 1010 266s 4min 26s 1111 8519s 2hr 22s Table 29 DC Servo Active Modes DC SERVO READBACK The current DC offset value for each Headphone output channel can be read from Regist...

Page 52: ...90 automatically controls VMID using a pop suppression circuit to avoid a step change in VMID this suppresses pop click noise which could otherwise occur By default the 2 x 5k VMID divider is selected...

Page 53: ...0 Headphone Output HPOUTR input stage enable 0 Disabled 1 Enabled For pop free operation this bit should be set as the first stage of the HPOUTR Enable sequence 2 1 VMID_RES 1 0 00 VMID Divider Enable...

Page 54: ...MIXOUTR_ENA 0 MIXOUTR Headphone Mixer Enable 0 Disabled 1 Enabled 3 SPKMIX_ENA 0 SPKMIX Speaker Mixer Enable 0 Disabled 1 Enabled R57 39h AntiPOP2 2 STARTUP_BIAS_ ENA 0 Enables the Start Up bias curre...

Page 55: ...tput driver When the temperature sensor is enabled the temperature status can be read from the TSHUT register bit Note that to prevent pops and clicks TSHUT_ENA and TSHUT_OPDIS should only be updated...

Page 56: ..._000P_0010_1101 29 1D Right Output Volume 0 0 0 0 0 0 0 HPOUT1_V U HPOUT1R_Z C HPOUT1R_ MUTE 0000_000P_0010_1101 34 22 SPKMIXL Attenuation 0 0 0 0 0 0 0 SPKMIX_MU TE 0000_0001_0000_0000 36 24 SPKOUT M...

Page 57: ...o 2 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 1 0000_1000_0000_0111 87 57 DC Servo 3 0000_0000_0000_0000 88 58 DC Servo Readback 0 0 0 0 0 0 0 0 0 0 0 0000_0000_0000_0000 89 59 DC Servo Readback 1 0 0 0 0 0 0 0 0...

Page 58: ...d be set as the first stage of the HPOUTR Enable sequence 3 OSC_ENA 0 CLK_SYS Oscillator Enable 0 Disabled 1 Enabled 2 1 VMID_RES 1 0 11 VMID Divider Enable and Select 00 VMID disabled for OFF mode 01...

Page 59: ...ABEL DEFAULT DESCRIPTION REFER TO R3 03h Power Managemen t 3 14 AGC_ENA 0 AGC Enable 0 Disabled 1 Enabled 8 SPKLVOL_EN A 0 Speaker PGA Enable 0 Disabled 1 Enabled Note that SPKMIXL and SPKLVOL are als...

Page 60: ...P and IN2N input pad VMID clamp 0 Clamp de activated 1 Clamp activated Register 17h IN2 Line Control REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO R24 18h IN1 Line Input A Volume 8 IN1_VU N...

Page 61: ...010 0dB 011 3 5dB 100 6dB 101 12dB 110 18dB 111 18dB IN1B Volume single ended mode 000 0dB 001 2 5dB 010 6dB 011 9 5dB 100 12dB 101 18dB 110 24dB 111 24dB Register 19h IN1 Line Input B Volume REGISTE...

Page 62: ...1 Mute 6 IN2B_ZC 0 IN2B PGA Zero Cross Control 0 Change gain immediately 1 Change gain on zero cross only 2 0 IN2B_VOL 2 0 011 IN2B Volume differential mode 000 6dB 001 3 5dB 010 0dB 011 3 5dB 100 6d...

Page 63: ...trol 0 Change gain immediately 1 Change gain on zero cross only 6 HPOUT1R_MU TE 0 Right Headphone Output PGA Mute 0 Un mute 1 Mute 5 0 HPOUT1R_VO L 5 0 10_1101 Right Headphone Output PGA Volume 57dB t...

Page 64: ...0dB Register 25h ClassD3 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO R38 26h Speaker Volume Left 8 SPKOUT_VU N A Speaker Output PGA Volume Update Writing a 1 to this bit will update the SP...

Page 65: ...2Fh Output Mixer3 8 MIXOUTL_MU TE 1 MIXOUTL Output mute 0 Un Mute 1 Mute 7 6 IN1A_MIXOUT L_VOL 1 0 00 IN1A to MIXOUTL volume control 00 0dB 01 6dB 10 9dB 11 12dB 3 2 IN2A_MIXOUT L_VOL 1 0 00 IN2A to M...

Page 66: ...nable 0 Disabled 1 Enabled 0 IN2B_TO_SPK MIX 0 IN2B to SPKMIX enable 0 Disabled 1 Enabled Register 36h Speaker Mixer REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO R57 39h AntiPOP2 3 VMID_BUF...

Page 67: ...0 0000 Time delay after executing this step Total time per step including execution 62 5us 2 WSEQ_DELAY 8 7 0 WSEQ_DATA 7 0 0000_0000 Data to be written in this sequence step When the data width is l...

Page 68: ...ue of 1 indicates that the DC Servo single correction is in progress 12 DCS_TRIG_SI NGLE_0 0 Writing 1 to this bit selects a single DC offset correction for HPOUT1L In readback a value of 1 indicates...

Page 69: ...0 DCS_TIMER_P ERIOD_01 3 0 1010 Time between periodic updates Time is calculated as 0 256s x 2 PERIOD 0000 Off 0001 0 52s 1010 266s 4min 26s 1111 8519s 2hr 22s Register 55h DC Servo 1 REGISTER ADDRES...

Page 70: ...DESCRIPTION REFER TO R90 5Ah DC Servo Readback 2 7 0 DCS_DAC_W R_VAL_0_RD 7 0 0000_0000 Readback value for HPOUT1L Two s complement format LSB is 0 25mV Range is 32mV to 31 75mV Register 5Ah DC Servo...

Page 71: ...ed and before the DC Offset cancellation is scheduled This bit should be set with at least 20us delay after HPOUT1L_ENA Register 60h Analogue HP 0 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER...

Page 72: ...imit Mode 0 Disabled 1 Enabled 12 AGC_PWR_AV G 0 AGC Power Measurement mode 0 Instantaneous power 1 RMS power 11 8 AGC_PWR_TH R 2 0 0000 AGC Power Limit Threshold Sets the output level at which Power...

Page 73: ...1200ms 6dB 010 1320ms 6dB 011 1680ms 6dB 100 2040ms 6dB 101 2760ms 6dB 110 4080ms 6dB 111 8160ms 6dB Register 63h AGC Control 1 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO R100 64h AGC Con...

Page 74: ...rnal components for WM9090 Note that the diagram does not include any components that are specific to the end application e g they do not include filtering on the speaker outputs assume filterless cla...

Page 75: ...onditions The applicable input impedance can be found in the Electrical Characteristics section of this datasheet INPUT IMPEDANCE MINIMUM CAPACITANCE FOR 20HZ PASS BAND 2k 4 F 15k 0 5 F 30k 0 27 F 60k...

Page 76: ...2 2 F ceramic SPKVDD 0 1 F ceramic see note VMIDC 2 2 F ceramic see text below Table 36 Power Supply Decoupling Capacitors Note 0 1 F is required with 2 2 F a guide to the total required power rail c...

Page 77: ...ate the audio signal This may be implemented using a 2 nd order LC or 1 st order RC filter or else may be achieved by using a loudspeaker whose internal inductance provides the required filter respons...

Page 78: ...ple if we know the speaker impedance is 8 and the desired cut off frequency is 20kHz then the optimum speaker inductance may be calculated as 8 loudspeakers typically have an inductance in the range 2...

Page 79: ...via a cable form it is recommended that a shielded twisted pair cable is used The shield should be connected to the main system with care taken to ensure ground loops are avoided Further reduction in...

Page 80: ...HIS DIMENSION INCLUDES STAND OFF HEIGHT A1 AND BACKSIDE COATING 3 A1 CORNER IS IDENTIFIED BY INK LASER MARK ON TOP PACKAGE 4 BILATERAL TOLERANCE ZONE IS APPLIED TO EACH SIDE OF THE PACKAGE BODY 5 e RE...

Page 81: ...or systems where malfunction can reasonably be expected to result in personal injury death or severe property or environmental damage Any use of products by the customer for such purposes is at the cu...

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