Wolfson WM8978 Manual Download Page 37

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Production Data

WM8978

PD, Rev 4.5, October 2011

REGISTER

ADDRESS

BIT LABEL DEFAULT

DESCRIPTION

7:4 ALCHLD

[3:0]

0000
(0ms)

ALC hold time before gain is
increased.
0000 = 0ms
0001 = 2.67ms
0010 = 5.33ms
0011 = 10.66ms
0100 = 21.32ms
0101 = 42.64ms
0110 = 85.28ms
0111 = 0.17s
1000 = 0.34s
1001 = 0.68s
1010 or higher = 1.36s

R34 (22h)
ALC Control
3

ALCMODE

Determines the ALC mode of
operation:
0 = ALC mode (Normal Operation)
1 = Limiter mode.

7:4 ALCDCY

[3:0]

0011
(26ms/6dB)

Decay (gain ramp-up) time
(ALCMODE ==0)
Per

step

Per
6dB

90% of
range

0000 410us 3.28ms 23.6ms
0001 820us 6.56ms 47.2ms
0010 1.64ms 13.1ms 94.5ms
… (time doubles with every step)
1010
or
higher

420ms 3.36s 24.2s

0011
(5.8ms/6dB)

Decay (gain ramp-up) time
(ALCMODE ==1)
Per

step

Per
6dB

90% of
range

0000 90.8us 726us

5.23ms

0001 182us  1.45ms  10.5ms
0010 363us  2.91ms  20.9ms
… (time doubles with every step)
1010 93ms  744ms 5.36s

3:0 ALCATK

[3:0]

0010
(3.3ms/6dB)

ALC attack (gain ramp-down) time
(ALCMODE == 0)
Per

step

Per
6dB

90% of
range

0000 104us  832us  6ms
0001 208us  1.66ms  12ms
0010 416us  3.33ms  24ms
… (time doubles with every step)
1010
or
higher

106ms 852ms 6.13s

0010
(726us/6dB)

ALC attack (gain ramp-down) time
(ALCMODE == 1)
Per

step

Per
6dB

90% of
range

0000 22.7us 182.4us

1.31ms

0001 45.4us 363us

2.62ms

0010 90.8us 726us

5.23ms

Summary of Contents for WM8978

Page 1: ...MHz The WM8978 operates at analogue supply voltages from 2 5V to 3 3V although the digital core can operate at voltages down to 1 71V to save power The speaker outputs and OUT3 4 line outputs can run...

Page 2: ...DE 17 CONTROL INTERFACE TIMING 2 WIRE MODE 18 INTERNAL POWER ON RESET CIRCUIT 19 DEVICE DESCRIPTION 21 INTRODUCTION 21 INPUT SIGNAL PATH 23 ANALOGUE TO DIGITAL CONVERTER ADC 30 INPUT LIMITER AUTOMATIC...

Page 3: ...ction Data WM8978 w PD Rev 4 5 October 2011 3 5 BAND EQUALISER 111 APPLICATION INFORMATION 115 RECOMMENDED EXTERNAL COMPONENTS 115 PACKAGE DIAGRAM 116 IMPORTANT NOTICE 117 ADDRESS 117 REVISION HISTORY...

Page 4: ...FORMATION ORDER CODE TEMPERATURE RANGE PACKAGE MOISTURE SENSITIVITY LEVEL PEAK SOLDERING TEMPERATURE WM8978CGEFL V 40 C to 100 C 32 lead QFN 5 x 5 mm Pb free MSL3 260 o C WM8978CGEFL RV 40 C to 100 C...

Page 5: ...SDIN Digital Input Output 3 Wire Control Interface Data Input 2 Wire Control Interface Data Input 18 MODE Digital Input Control Interface Selection 19 AUXL Analogue input Left Auxillary input 20 AUXR...

Page 6: ...e barrier bag MSL3 out of bag storage for 168 hours at 30 C 60 Relative Humidity Supplied in moisture barrier bag The Moisture Sensitivity Level for each package type is specified in Ordering Informat...

Page 7: ...grammable Gain Step Size Guaranteed monotonic 0 75 dB Mute Attenuation 120 dB Selectable Input Gain Boost 0 20dB Gain Boost on PGA input Boost disabled 0 dB Boost enabled 20 dB Maximum Gain from AUXL...

Page 8: ...al to Noise Ratio Note 6 SNR A weighted 0dB gain 85 95 dB Total Harmonic Distortion Note 7 THD 3dBFS input 84 74 dB Channel Separation Note 9 1kHz input signal 110 dB Digital to Analogue Converter DAC...

Page 9: ...RL 8 90 dB Power Supply Rejection Ratio 50Hz 22kHz PSRR RL 8 BTL 80 dB RL 8 BTL SPKVDD 5V boost 69 dB OUT3 OUT4 Outputs with 10k 50pF load Full scale output voltage 0dB gain Note 10 OUT3BOOST 0 OUT4BO...

Page 10: ...times scale proportionally with MCLK 6 Signal to noise ratio dB SNR is a measure of the difference in level between the full scale output and the output with no signal applied No Auto zero or Automut...

Page 11: ...Production Data WM8978 w PD Rev 4 5 October 2011 11 SPEAKER OUTPUT THD VERSUS POWER...

Page 12: ...rrent will fall to nearer 15uA when thermal shutdown sensor is disabled Table 1 Power Consumption ESTIMATING SUPPLY CURRENT When either the DAC or ADC is enabled approximately 7mA will be drawn from D...

Page 13: ...settings ROUT1EN 0 4 LOUT1EN 0 4 BOOSTENR 0 2 BOOSTENL 0 2 INPPGAENR 0 2 INPPGAENL 0 2 ADCENR 2 6 x64 ADCOSR 0 4 9 x128 ADCOSR 1 ADCENL 2 6 x64 ADCOSR 0 4 9 x128 ADCOSR 1 OUT4EN 0 2 OUT3EN 0 2 LOUT2EN...

Page 14: ...WM8978 Production Data w PD Rev 4 5 October 2011 14 AUDIO PATHS OVERVIEW...

Page 15: ...ND 0V TA 25 o C PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT System Clock Timing Information MCLK cycle time TMCLKY MCLK SYSCLK 256fs 81 38 ns MCLK input to PLL Note 1 20 ns MCLK duty cycle TMCLKDS 60...

Page 16: ...E TIMING SLAVE MODE Figure 3 Digital Audio Data Timing Slave Mode Test Conditions DCVDD 1 8V DBVDD AVDD SPKVDD 3 3V DGND AGND SPKGND 0V TA 25 o C Slave Mode fs 48kHz MCLK 256fs 24 bit data unless othe...

Page 17: ...ata unless otherwise stated PARAMETER SYMBOL MIN TYP MAX UNIT Program Register Input Information SCLK rising edge to CSB rising edge tSCS 80 ns SCLK pulse cycle time tSCY 200 ns SCLK pulse width low t...

Page 18: ...8kHz MCLK 256fs 24 bit data unless otherwise stated PARAMETER SYMBOL MIN TYP MAX UNIT Program Register Input Information SCLK Frequency 0 526 kHz SCLK Low Pulse Width t1 1 3 us SCLK High Pulse Width t...

Page 19: ...uence where AVDD is Powered before DVDD Figure 7 shows a typical power up sequence where AVDD comes up first When AVDD goes above the minimum threshold Vpora there is enough voltage for the circuit to...

Page 20: ...PORB is asserted low whenever DVDD drops below the minimum threshold Vpord_off SYMBOL MIN TYP MAX UNIT Vpora 0 4 0 6 0 8 V Vpora_on 0 9 1 2 1 6 V Vpora_off 0 4 0 6 0 8 V Vpord_on 0 5 0 7 0 9 V Vpord_...

Page 21: ...ng volume constant LINE INPUTS AUXL AUXR The inputs AUXL and AUXR can be used as a stereo line input or as an input for warning tones or beeps etc These inputs can be summed into the record paths alon...

Page 22: ...generate alternative clocks which may then be output on the GPIO pins and used elsewhere in the system POWER CONTROL The design of the WM8978 has given much attention to power consumption without comp...

Page 23: ...re are two auxiliary input pins which can be fed into to the input boost mix stage as well as driving into the output path A bypass path exists from the output of the boost mix stage into the output l...

Page 24: ...P2INPPGA 1 Connect RIP pin to right channel input PGA amplifier positive terminal 0 RIP not connected to input PGA 1 right channel input PGA amplifier positive terminal connected to RIP constant input...

Page 25: ...lume control 5 0 INPPGAVOLR 010000 Right channel input PGA volume 000000 12dB 000001 11 25db 010000 0dB 111111 35 25dB 6 INPPGAMUTER 0 Mute control for right channel input PGA 0 Input PGA not muted no...

Page 26: ...while the signal is a non zero value an audible click can occur as shown in Figure 11 Figure 11 Click Noise During Volume Update In order to prevent this click noise a zero cross function is provided...

Page 27: ...on If there is a long period where no zero crossing occurs a timeout circuit in the WM8978 will automatically update the volume The volume updates will occur between one and two timeout periods depend...

Page 28: ...dual gain boost adjust as shown in Figure 14 Figure 14 Input Boost Stage The input PGA paths can have a 20dB boost PGABOOSTL R 1 a 0dB pass through PGABOOSTL R 0 or be completely isolated from the inp...

Page 29: ...l 2 0 AUXR2BOOSTVOL 000 Controls the auxiliary amplifier to the right channel input boost stage 000 Path disabled disconnected 001 12dB gain through boost stage 010 9dB gain through boost stage 111 6d...

Page 30: ...0 9 AVDD 1 0 65 AVDD Table 11 Microphone Bias Voltage Control The internal MICBIAS circuitry is shown in Figure 15 Note that the maximum source current capability for MICBIAS is 3mA The external bias...

Page 31: ...ves lowest power operation and when ADCOSR 1 the oversample rate is 128x which gives best performance REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R14 ADC Control 0 ADCLPOL 0 ADC left channel polari...

Page 32: ...1 010 SR 001 000 fs kHz 8 11 025 12 16 22 05 24 32 44 1 48 000 82 113 122 82 113 122 82 113 122 001 102 141 153 102 141 153 102 141 153 010 131 180 196 131 180 196 131 180 196 011 163 225 245 163 225...

Page 33: ...lly only update when one of the NFU bits is set high R28 Notch Filter 2 6 0 NFA0 6 0 0 Notch filter a0 coefficient bits 6 0 8 NFU 0 Notch filter update The notch filter values used internally only upd...

Page 34: ...tan 1 0 9869949627 cos 1 0 0 1 w a a 1308996939 0 cos 9869949627 0 1 1 969995945 NFA0 a0 x 213 8085 rounded to nearest whole number NFA1 a1 x 212 8069 rounded to nearest whole number These values are...

Page 35: ...26 5dB 0 5dB steps up to 1111 1111 0dB 8 ADCVU Not latched ADC left and ADC right volume do not update until a 1 is written to ADCVU in reg 15 or 16 R16 Right channel ADC Digital Volume 7 0 ADCVOLR 7...

Page 36: ...e ALCMODE register normal mode and peak limiter mode The ALC limiter function is enabled by setting the register bit R32 8 ALCSEL REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R32 20h ALC Control 1 2...

Page 37: ...28ms 23 6ms 0001 820us 6 56ms 47 2ms 0010 1 64ms 13 1ms 94 5ms time doubles with every step 1010 or higher 420ms 3 36s 24 2s 0011 5 8ms 6dB Decay gain ramp up time ALCMODE 1 Per step Per 6dB 90 of ran...

Page 38: ...sters When the ALC is disabled the input PGA remains at the last controlled value of the ALC An input gain update must be made by writing to the INPPGAVOLL R register bits NORMAL MODE In normal mode t...

Page 39: ...ion ALC LIMITER MODE INITIALISATION SEQUENCE In order to properly initialise the ALC function the following sequence of register writes is required 1 Set INPPGAVOLL to the required input PGA gain R45...

Page 40: ...pecified by the SR register NORMAL MODE ALCMODE 0 Normal Mode ALCATK tATK tATK6dB tATK90 0000 104 s 832 s 6ms 0001 208 s 1 66ms 12ms 0010 416 s 3 33ms 24ms 0011 832 s 6 66ms 48ms 0100 1 66ms 13 3ms 96...

Page 41: ...69ms 1000 23 2ms 186ms 1 34s 1001 46 5ms 372ms 2 68s 1010 93ms 744ms 5 36s Attack Time s Table 19 ALC Limiter Mode Attack and Decay times MINIMUM AND MAXIMUM GAIN The ALCMIN and ALCMAX register bits s...

Page 42: ...000 12 001 6 010 0 011 6 100 12 101 18 110 24 111 30 Table 22 ALC Min Gain Values Note that if the ALC gain setting strays outside the ALC operating range either by starting the ALC outside of the ra...

Page 43: ...REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R33 ALC Control 2 7 4 ALCHLD 0000 ALC hold time before gain is increased Table 23 ALC Hold Time If the hold time is exceeded this indicates that the sig...

Page 44: ...w PD Rev 4 5 October 2011 44 Figure 21 ALC Hold Time ALCHLD tHOLD s 0000 0 0001 2 67ms 0010 5 34ms 0011 10 7ms 0100 21 4ms 0101 42 7ms 0110 85 4ms 0111 171ms 1000 342ms 1001 684ms 1010 1 37s Table 24...

Page 45: ...against a noise gate threshold NGTH The noise gate cuts in when Signal level at ADC dBFS NGTH dBFS PGA gain dB Mic Boost gain dB This is equivalent to Signal level at input pin dBFS NGTH dBFS The PGA...

Page 46: ...WM8978 Production Data w PD Rev 4 5 October 2011 46 Figure 22 ALC Operation Above Noise Gate Threshold...

Page 47: ...The mixers and output drivers can be separately enabled by individual control bits see Analogue Outputs Thus it is possible to utilise the analogue mixing and amplification provided by the WM8978 irr...

Page 48: ...enabled gradually attenuates the volume of the digital signal to zero When disabled the gain will ramp back up to the digital gain setting This function is enabled by default To play back an audio si...

Page 49: ...dB Right DAC Digital Volume Control 0000 0000 Digital Mute 0000 0001 127dB 0000 0010 126 5dB 0 5dB steps up to 1111 1111 0dB 8 DACVU Not latched DAC left and DAC right volume do not update until a 1 i...

Page 50: ...hold the signal is amplified at a specific decay rate controlled by LIMDCY register bits until a gain of 0dB is reached Both threshold levels are controlled by the LIMLVL register bits The upper thres...

Page 51: ...s 1010 96ms 1011 to 1111 192ms 7 4 LIMDCY 0011 Limiter Decay time per 6dB gain change for 44 1kHz sampling Note that these will scale proportionally with sample rate 0000 750us 0001 1 5ms 0010 3ms 001...

Page 52: ...DAC path Table 30 EQ and 3D Enhancement DAC or ADC Path Select The equaliser consists of low and high frequency shelving filters Band 1 and 5 and three peak filters for the centre bands Each has adjus...

Page 53: ...4 0 EQ4G 01100 0dB Band 4 Gain Control See Table 36 for details 6 5 EQ4C 01 Band 4 Centre Frequency 00 1 8kHz 01 2 4kHz 10 3 2kHz 11 4 1kHz 8 EQ4BW 0 Band 4 Bandwidth Control 0 narrow bandwidth 1 wid...

Page 54: ...onfigured as a stereo line out OUT3 is left output and OUT4 is right output OUT4 can also be used to provide a mono mix of left and right channels LOUT2 ROUT2 OUT3 and OUT4 are supplied from SPKVDD an...

Page 55: ...Production Data WM8978 w PD Rev 4 5 October 2011 55 Figure 26 Left Right Output Channel Mixers...

Page 56: ...ot selected 1 selected 4 2 BYPLMIXVOL 000 Left bypass volume control to output channel mixer 000 15dB 001 12dB 101 0dB 110 3dB 111 6dB 5 AUXL2LMIX 0 Left Auxiliary input to left channel output mixer 0...

Page 57: ...ment 3 2 LMIXEN 0 Left output channel mixer enable 0 disabled 1 enabled 3 RMIXEN 0 Right output channel mixer enable 0 disabled 1 enabled Table 38 Left and Right Output Mixer Control HEADPHONE OUTPUTS...

Page 58: ...0000 57dB 111001 0dB 111111 6dB 8 HPVU Not latched LOUT1 and ROUT1 volumes do not update until a 1 is written to HPVU in reg 52 or 53 R53 ROUT1 Volume control 7 ROUT1ZC 0 Headphone volume zero cross e...

Page 59: ...mode OUT3BOOST OUT4BOOST 1 then the VMID value of these outputs will be equal to 1 5xAVDD 2 and will not match the VMID of the headphone drivers Do not use the DC coupled output mode in this configur...

Page 60: ...WM8978 Production Data w PD Rev 4 5 October 2011 60 Figure 29 Speaker Outputs LOUT2 and ROUT2...

Page 61: ...ts and can be any combination of the DAC output the Bypass path output of the input boost stage and the AUX input The LOUT2 ROUT2 volume is controlled by the LOUT2VOL ROUT2VOL register bits Gains over...

Page 62: ...RPGA2INV 0 Mute input to INVROUT2 mixer 4 INVROUT2 0 Invert ROUT2 output 3 1 BEEPVOL 000 AUXR input to ROUT2 inverter gain 000 15dB 111 6dB 0 BEEPEN 0 0 mute AUXR beep input 1 enable AUXR beep input T...

Page 63: ...mixer for OUT3 and one for OUT4 as shown in Figure 31 The OUT3 and OUT4 output stages are powered from SPKVDD and SPKGND The individually controllable outputs also incorporate an optional 1 5x boost...

Page 64: ...t DAC mixer to OUT4 0 disabled 1 enabled 3 LDAC2OUT4 0 Left DAC to OUT4 0 disabled 1 enabled 2 BYPR2OUT4 0 Right ADC input to OUT4 0 disabled 1 enabled 1 RMIX2OUT4 0 Right DAC mixer to OUT4 0 disabled...

Page 65: ...1 DC AVDD 2 1 OUT4 output gain 1 5 DC 1 5 x AVDD 2 R1 Power management 1 8 BUFDCOPEN 0 Dedicated buffer for DC level shifting output stages when in 1 5x gain boost configuration 0 Buffer disabled 1 Bu...

Page 66: ...er path For example DACL can be directly input to the OUT3 mixer giving a 180 phase shift at the OUT3 mixer output However if DACL is input to the OUT3 mixer via the left mixer an additional phase shi...

Page 67: ...UT1 and LOUT2 ROUT2 and OUT4 OUT3 Speaker boost enabled 0 0 0 1 0 0 0 1 0 1 0 1 0 1 0 1 5 0 1 5 Stereo DAC playback to LOUT1 ROUT1 and LOUT2 ROUT2 and OUT4 OUT3 OUT3 and OUT4 boost enabled 0 0 0 0 1 1...

Page 68: ...ON 0 OFF Table 49 Output Stages Power Management Control THERMAL SHUTDOWN The speaker outputs can drive very large currents To protect the WM8978 from overheating a thermal shutdown circuit is includ...

Page 69: ...tput of the DC level shift buffer at 1 5xAVDD 2 when disabled Figure 35 summarises the tie off options for the speaker and mono output pins Figure 35 Unused Input Output Pin Tie off Buffers L ROUT2EN...

Page 70: ...section for timing information MASTER AND SLAVE MODE OPERATION The WM8978 audio interface may be configured as either master or slave As a master interface device the WM8978 generates BCLK and LRC and...

Page 71: ...unused BCLK cycles after each LRC transition Figure 37 Right Justified Audio Interface assuming n bit word length In I 2 S mode the MSB is available on the second rising edge of BCLK following a LRC t...

Page 72: ...selectable by LRP following a rising edge of LRC Right channel data immediately follows left channel data Depending on word length BCLK frequency and sample rate there may be unused BCLK cycles betwe...

Page 73: ...ode A B select 1 MSB is available o n 1st BCLK rising edge after LRC rising edge mode B 0 MSB is available o n 2nd BCLK rising edge after LRC rising edge mode A 8 BCP BCLK polarity 0 normal 1 inverted...

Page 74: ...output under control of CLKSEL 000 divide by 1 001 divide by 1 5 010 divide by 2 011 divide by 3 100 divide by 4 101 divide by 6 110 divide by 8 111 divide by 12 8 CLKSEL 1 Controls the source of the...

Page 75: ...0 48kHz 001 32kHz 010 24kHz 011 16kHz 100 12kHz 101 8kHz 110 111 reserved Table 55 Sample Rate Control MASTER CLOCK AND PHASE LOCKED LOOP PLL The WM8978 has an on chip phase locked loop PLL circuit th...

Page 76: ...by 4 in the PLL and a selectable divide by N after the PLL which should be set to divide by 2 to meet this requirement Enabling the divide by 2 sets the required f2 4 x 2 x 12 288MHz 98 304MHz R 98 30...

Page 77: ...09 9 1F76F7 19 8 12 288 98 304 2 2 9 929697 9 EE009E 24 11 29 90 3168 2 2 7 5264 7 86C226 24 12 288 98 304 2 2 8 192 8 3126E8 26 11 29 90 3168 2 2 6 947446 6 F28BD4 26 12 288 98 304 2 2 7 561846 7 8FD...

Page 78: ...ded by the G 711 standard all 8 bits are inverted for law all even data bits are inverted for A law The data will be transmitted as the first 8 MSB s of data Companding converts 13 bits law or 12 bits...

Page 79: ...PUT The WM8978 has three dual purpose input output pins CSB GPIO1 CSB GPIO pin L2 GPIO2 Left channel line input headphone detection input R2 GPIO3 Right channel line input headphone detection input Th...

Page 80: ...output enables from toggling multiple times due to input glitches This de bounce circuit is clocked from a slow clock with period 2 21 x MCLK and is enabled by the SLOWCLKEN bit Notes 1 The SLOWCLKEN...

Page 81: ...l via the normal output enables found in Table 49 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R9 GPIO control 5 4 JD_SEL 00 Pin selected as jack detection input 00 GPIO1 01 GPIO2 10 GPIO3 11 Reserv...

Page 82: ...device address and data will follow All devices on the 2 wire bus respond to the start condition and shift in the next eight bits on SDIN 7 bit address Read Write bit MSB first If the device address...

Page 83: ...with lower distortion If SPKVDD is lower than AVDD the output signal may be clipped DCVDD Digital core supply powers all digital functions except the audio and control interfaces DCVDD can range from...

Page 84: ...R1 5 Set SPKBOOST 1 in register R49 6 Set VMIDSEL 1 0 to required value in register R1 Wait for the VMID supply to settle Refer notes 1 and 2 7 Set L RMIXEN 1 and DACENL R 1 in register R3 8 Set BIAS...

Page 85: ...5 boost mode will cause the VMID voltage to drop to AVDD 2 midrail level and cause an output pop In addition to the power on sequence it is recommended that the zero cross functions are used when cha...

Page 86: ...is enabled there will be LSB data bit activity on the ADCDAT pin due to system noise but no significant digital output will be present 4 The VMIDSEL and BIASEN bits must be set to enable analogue inpu...

Page 87: ...p noise on the analogue outputs The same is also true if the DACDAT is removed at a non zero value and no mute function has been applied to the signal beforehand 3 The lineout discharge time tline_mid...

Page 88: ...e select 0 64x lowest power 1 128x best SNR Table 66 ADC and DAC Oversampling Rate Selection VMID The analogue circuitry will not work when VMID is disabled VMIDSEL 1 0 00b The impedance of the VMID r...

Page 89: ...tect Control JD_EN1 JD_EN0 000 14 0E ADC Control HPFEN HPFAPP HPFCUT ADCOSR 128 0 ADCRPOL ADCLPOL 100 15 0F Left ADC Digital Vol ADCVU ADCVOLL 0FF 16 10 Right ADC Digital Vol ADCVU ADCVOLR 0FF 18 12 E...

Page 90: ...OOST OUT3 BOOST SPK BOOST TSDEN VROI 002 50 32 Left mixer ctrl AUXLMIXVOL AUXL2LMIX BYPLMIXVOL BYPL2LMIX DACL2LMIX 001 51 33 Right mixer ctrl AUXRMIXVOL AUXR2RMI X BYPRMIXVOL BYPR2RMIX DACR2RMIX 001 5...

Page 91: ...Master Clock and Phase Locked Loop PLL 4 MICBEN 0 Microphone Bias Enable 0 OFF high impedance output 1 ON Input Signal Path 3 BIASEN 0 Analogue amplifier bias control 0 disabled 1 enabled Power Manage...

Page 92: ...d 1 enabled Power Management 3 RMIXEN 0 Right output channel mixer enable 0 disabled 1 enabled Analogue Outputs 2 LMIXEN 0 Left output channel mixer enable 0 disabled 1 enabled Analogue Outputs 1 DACE...

Page 93: ...e operation Data appears in left phase of LRC Digital Audio Interfaces 5 05h 8 6 000 Reserved 5 WL8 0 Companding Control 8 bit mode 0 off 1 device operates in 8 bit mode Digital Audio Interfaces 4 3 D...

Page 94: ...configures the coefficients for the internal digital filters 000 48kHz 001 32kHz 010 24kHz 011 16kHz 100 12kHz 101 8kHz 110 111 reserved Audio Sample Rates 0 SLOWCLKEN 0 Slow clock enable Used for bot...

Page 95: ...Output Signal Path 1 DACPOLR 0 Right DAC output polarity 0 non inverted 1 inverted 180 degrees phase shift Output Signal Path 0 DACPOLL 0 Left DAC output polarity 0 non inverted 1 inverted 180 degree...

Page 96: ...to Digital Converter ADC 3 ADCOSR 128 0 ADC oversample rate select 0 64x lowest power 1 128x best SNR Power Management 2 0 Reserved 1 ADCRPOL 0 ADC right channel polarity adjust 0 normal 1 inverted A...

Page 97: ...nal Path 4 0 EQ2G 01100 EQ Band 2 Gain Control See Table 36 for details Output Signal Path 20 14h 8 EQ3BW 0 EQ Band 3 Bandwidth Control 0 narrow bandwidth 1 wide bandwidth Output Signal Path 7 0 Reser...

Page 98: ...10 768ms Output Signal Path 3 0 LIMATK 0010 DAC Limiter Attack time per 6dB gain change for 44 1kHz sampling Note that these will scale with sample rate 0000 94us 0001 188s 0010 375us 0011 750us 0100...

Page 99: ...Digital Converter ADC 29 1Dh 8 NFU 0 Notch filter update The notch filter values used internally only update when one of the NFU bits is set high Analogue to Digital Converter ADC 7 0 Reserved 6 0 NFA...

Page 100: ...Automatic Level Control ALC 34 22h 8 ALCMODE 0 Determines the ALC mode of operation 0 ALC mode 1 Limiter mode Input Limiter Automatic Level Control ALC 7 4 ALCDCY 3 0 0011 Decay gain ramp up time ALCM...

Page 101: ...se Locked Loop PLL 3 0 PLLN 3 0 1000 Integer N part of PLL input output frequency ratio Use values greater than 5 and less than 13 Master Clock and Phase Locked Loop PLL 37 25h 8 6 000 Reserved 5 0 PL...

Page 102: ...tive terminal connected to RIP constant input impedance Input Signal Path 3 0 Reserved 2 L2_2INPPGA 0 Connect L2 pin to left channel input PGA positive terminal 0 L2 not connected to input PGA 1 L2 co...

Page 103: ...el input PGA volume 000000 12dB 000001 11 25db 010000 0dB 111111 35 25dB Input Signal Path 47 2Fh 8 PGABOOSTL 1 Boost enable for left channel input PGA 0 PGA output has 0dB gain through input BOOST st...

Page 104: ...cted 1 selected Analogue Outputs 5 DACR2LMIX 0 Right DAC output to left output mixer 0 not selected 1 selected Analogue Outputs 4 OUT4BOOST 0 0 OUT4 output gain 1 DC AVDD 2 1 OUT4 output gain 1 5 DC 1...

Page 105: ...puts 5 AUXR2RMIX 0 Right Auxiliary input to right channel output mixer 0 not selected 1 selected Analogue Outputs 4 2 BYPRMIXVOL 000 Right bypass volume control to output channel mixer 000 15dB 001 12...

Page 106: ...54 or 55 Analogue Outputs 7 LOUT2ZC 0 Speaker volume zero cross enable 1 Change gain on zero cross only 0 Change gain immediately Analogue Outputs 6 LOUT2MUTE 0 Left speaker output mute 0 Normal opera...

Page 107: ...57 39h 8 7 00 Reserved 6 OUT4MUTE 0 0 Output stage outputs OUT4 mixer 1 Output stage muted drives out VMID Can be used as VMID buffer in this mode Analogue Outputs 5 HALFSIG 0 0 OUT4 normal output 1...

Page 108: ...ADC High Pass Filter High Pass Filter Corner Frequency 3dB 3 7 Hz 0 5dB 10 4 0 1dB 21 6 DAC Filter Passband 0 035dB 0 0 454fs 6dB 0 5fs Passband Ripple 0 035 dB Stopband 0 546fs Stopband Attenuation...

Page 109: ...e 128xOSR 160 140 120 100 80 60 40 20 0 20 0 0 5 1 1 5 2 2 5 Frequency fs Response dB 2 6 2 65 2 7 2 75 2 8 2 85 2 9 2 95 3 3 05 0 0 05 0 1 0 15 0 2 0 25 0 3 0 35 0 4 0 45 0 5 Frequency fs Response dB...

Page 110: ...0 5 0 5 10 15 20 25 30 35 40 45 Frequency Hz Response dB Figure 54 ADC Highpass Filter Response HPFAPP 0 60 50 40 30 20 10 0 10 0 200 400 600 800 1000 1200 Frequency Hz Response dB 80 70 60 50 40 30 2...

Page 111: ...0 0 10 1 10 2 10 3 10 4 10 5 15 10 5 0 5 10 15 Frequency Hz Magnitude dB 10 1 10 0 10 1 10 2 10 3 10 4 10 5 15 10 5 0 5 10 15 Frequency Hz Magnitude dB Figure 58 EQ Band 1 Low Frequency Shelf Filter C...

Page 112: ...dB 10 1 10 0 10 1 10 2 10 3 10 4 10 5 15 10 5 0 5 10 15 Frequency Hz Magnitude dB Figure 63 EQ Band 3 Peak Filter Centre Frequencies EQ3B Figure 64 EQ Band 3 Peak Filter Gains for Lowest Cut off Freq...

Page 113: ...Q3B Figure 67 EQ Band 4 Peak Filter Gains for Lowest Cut off Frequency EQ4BW 0 10 2 10 1 10 0 10 1 10 2 10 3 10 4 15 10 5 0 5 10 15 Frequency Hz Magnitude dB Figure 68 EQ Band 4 EQ3BW 0 EQ3BW 1 10 1 1...

Page 114: ...eously The blue traces show each band lowest cut off centre frequency with 12dB gain The red traces show the cumulative effect of all bands with 12dB gain and all bands 12dB gain with EqxBW 0 for the...

Page 115: ...Production Data WM8978 w PD Rev 4 5 October 2011 115 APPLICATION INFORMATION RECOMMENDED EXTERNAL COMPONENTS Figure 72 Recommended External Component Diagram...

Page 116: ...HALL CONFORM TO JEDEC 95 1 SPP 002 5 COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS 6 REFER TO APPLICATION NOTE WAN_0118 FOR FURTHER INFORMATION REGARDING PCB FOOTPRINTS AN...

Page 117: ...ms where malfunction can reasonably be expected to result in personal injury death or severe property or environmental damage Any use of products by the customer for such purposes is at the customer s...

Page 118: ...REVISION HISTORY DATE REV ORIGINATOR CHANGES 26 09 11 4 5 JMacD Order codes changed from WM8978GEFL V and WM8978GEFL RV to WM8978CGEFL V and WM8978CGEFL RV to reflect change to copper wire bonding 26...

Page 119: ...Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery Lifecycle Information Cirrus Logic WM8978CGEFL V WM8978CGEFL RV WM8978GEFL V...

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