Production Data
WM8978
w
PD, Rev 4.5, October 2011
17
CONTROL INTERFACE TIMING – 3-WIRE MODE
Figure 4 Control Interface Timing – 3-Wire Serial Control Mode
Test Conditions
DCVDD = 1.8V, DBVDD = AVDD = SPKVDD = 3.3V, DGND = AGND = SPKGND = 0V, T
A
=+25
o
C, Slave Mode, fs=48kHz,
MCLK = 256fs, 24-bit data, unless otherwise stated.
PARAMETER SYMBOL
MIN
TYP
MAX
UNIT
Program Register Input Information
SCLK rising edge to CSB rising edge
t
SCS
80
ns
SCLK pulse cycle time
t
SCY
200
ns
SCLK pulse width low
t
SCL
80
ns
SCLK pulse width high
t
SCH
80
ns
SDIN to SCLK set-up time
t
DSU
40
ns
SCLK to SDIN hold time
t
DHO
40
ns
CSB pulse width low
t
CSL
40
ns
CSB pulse width high
t
CSH
40
ns
CSB rising to SCLK rising
t
CSS
40
ns
Pulse width of spikes that will be suppressed
t
ps
0
5
ns
Summary of Contents for WM8978
Page 11: ...Production Data WM8978 w PD Rev 4 5 October 2011 11 SPEAKER OUTPUT THD VERSUS POWER...
Page 14: ...WM8978 Production Data w PD Rev 4 5 October 2011 14 AUDIO PATHS OVERVIEW...
Page 55: ...Production Data WM8978 w PD Rev 4 5 October 2011 55 Figure 26 Left Right Output Channel Mixers...
Page 60: ...WM8978 Production Data w PD Rev 4 5 October 2011 60 Figure 29 Speaker Outputs LOUT2 and ROUT2...