Wolfson WM8978, Manual, Page: 101 / 119

Production Data
WM8978
w
PD, Rev 4.5, October 2011
101
REGISTER
ADDRESS
BIT LABEL DEFAULT DESCRIPTION REFER TO
1010
or
higher 106ms 852ms 6.13s
0010 ALC attack (gain ramp-down) time
(ALCMODE == 1)
Per step Per 6dB 90% of range
0000 22.7us 182us 1.31ms
0001 45.4us 363us 2.62ms
0010 90.8us 726us 5.23ms
… (time doubles with every step)
1010 23.2ms 186ms 1.34s
35 (23h) 8:4 00000 Reserved
3 NGEN 0 ALC Noise gate function enable
1 = enable
0 = disable Input Limiter/
Automatic
Level Control
(ALC)
2:0 NGTH 000 ALC Noise gate threshold:
000=-39dB
001=-45dB
010=-51db
… (6dB steps)
111=-81dB Input Limiter/
Automatic
Level Control
(ALC)
36 (24h) 8:5 0000 Reserved
4 PLL
PRESCALE
0 0 = MCLK input not divided (default)
1 = Divide MCLK by 2 before input to PLL Master Clock
and Phase
Locked Loop
(PLL)
3:0 PLLN[3:0] 1000 Integer (N) part of PLL input/output frequency
ratio. Use values greater than 5 and less than
13. Master Clock
and Phase
Locked Loop
(PLL)
37 (25h) 8:6 000 Reserved
5:0 PLLK[23:18] 01100 Fractional (K) part of PLL1 input/output
frequency ratio (treat as one 24-digit binary
number). Master Clock
and Phase
Locked Loop
(PLL)
38 (26h) 8:0 PLLK[17:9] 010010011 Fractional (K) part of PLL1 input/output
frequency ratio (treat as one 24-digit binary
number). Master Clock
and Phase
Locked Loop
(PLL)
39 (27h) 8:0 PLLK[8:0] 011101001 Fractional (K) part of PLL1 input/output
frequency ratio (treat as one 24-digit binary
number). Master Clock
and Phase
Locked Loop
(PLL)
40 (28h) 8:0 00000000 Reserved
41 (29h) 8:4 00000 Reserved
3:0 DEPTH3D 0000 Stereo depth
0000: 0% (minimum 3D effect)
0001: 6.67%
....
1110: 93.3%
1111: 100% (maximum 3D effect) 3D Stereo
Enhancement
43 (2Bh) 8:6 000 Reserved
5 MUTERPGA2INV 0 Mute input to INVROUT2 mixer Analogue
Outputs