POL0- POL2
- These reg is ters are ac ces si ble when page 1 is se lected. They al low in ter rupt po lar ity
se lec tion on a port- by- port and bit- by- bit ba sis. Writ ing a '1' to a bit po si tion se lects the ris ing edge
de tec tion in ter rupts while writ ing a '0' to a bit po si tion se lects fal ling edge de tec tion in ter rupts.
ENAB0- ENAB2
- These reg is ters are ac ces si ble when page 2 is se lected. They al low for port- by-
port and bit- by- bit ena bling of the edge de tec tion in ter rupts. When set to a '1' the edge de tec tion
in ter rupt is en abled for the cor re spond ing port and bit. When cleared to a '0' the bit's edge de tec tion
in ter rupt is dis abled. Note that this reg is ter can be used to in di vidu ally clear a pend ing in ter rupt by
dis abling and reena bling the pend ing in ter rupt.
INT_ID0 - INT_ID2
- These reg is ters are ac ces si ble when page 3 is se lected. They are used to
iden tify cur rently pend ing edge in ter rupts. A bit when read as a '1' in di cates that an edge of the po lar ity
pro grammed into the cor re spond ing po lar ity reg is ter has been rec og nized. Note that a write to this
reg is ter (value ig nored) clears ALL of the pend ing in ter rupts in this reg is ter.
2.22
VGA Con figu ra tion
The EBC-LP uses a fourth generation CRT/Flat panel Super VGA controller. It supports standard
VGA output as well as a variety of Flat Panel Displays using optional Flat Panel Adapter (FPA) kits.
The video on the EBC-LP uses the Asiliant 69000 series of high performance VGA controllers. The
Asiliant controller supports standard and super-VGA as well as Color and Monochrome panels with 8,
9, 12, 15, 16, 18, 24 and 36-bit interfaces. WinSystems provides flat panel support through a series of
Flat Panel kits. Contact your WinSystems Applications Engineer for the most current list of available
FPA’s and supported panels.
Details regarding interfacing to specific Flat Panels is not provided in this manual but should be
referenced in the documentation accompanying the FPA kit. Attempted connection to any flat panel not
directly supported by a WinSystems FPA module is at the user’s risk and extreme care should be
exercised to avoid damaging or destroying the panel.
HAZARD WARNING:
LCD panels can require a high voltage for the panel backlight. This high-
frequency voltage can exceed 1000 volts and can present a shock hazard. Care should be taken when
wiring or handling the inverter output. To avoid danger of shock and to avoid damaging fragile and
expensive panels, make all connection changes with power removed.
Note:
J5 must be jumpered 1-2 for Sharp type panels, and 2-3 for NEC type panels. Jumper
positioning is shown on the following page. An example jumpering for NEC panels is shown below.
Page 2-22
EBC-LP OPERATIONS MANUAL
030530
WinSystems
- "The Embedded Authority"
o
1
o
2
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3
J5
Panel Backlight Enable
Summary of Contents for EBC-LP
Page 68: ...APPENDIX C Mechanical Drawing...
Page 69: ......
Page 70: ......
Page 71: ...APPENDIX D WS16C48 I O Routines and Sample Program Listings...
