Winbond W928C73 Instructions Manual Download Page 8

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Preliminary W928C73

- 8 -

Descriptions Of Special Function Registers(SFRS)

ADDRESS

/NAME

BIT

BIT NAME

R/W

INITIAL

FUNCTION

No use

Key_2

Key_2 input. A corresponding
key_INT(INT3_3) can be enabled.

Key_1

Key_1 input. A corresponding
key_INT(INT3_3) can be enabled.

Key_0

Key_0 input. A corresponding
key_INT(INT3_3) can be enabled.

DEC_ADDT

Matched Unmatched

POCSAG address matched flag. A
corresponding INT(INT2) could be setup.

F_ADR

Flash ROM serial address output

DEC_

SYNVAL

SYNC

Lost SYNC

Decoder synchronization condition

80H/P0

F_data R/W

Flash ROM data I/O

81H/SP

B7~0

SP R/W

00000111 Stack pointer address. Always points to

top of the stack.

82H/DPL

B7~0

DPL R/W

00000000 Low byte of 16 bit data pointer

83H/DPH

B7~0

DPH R/W

00000000 High byte of 16 bit data pointer

84H/DPL1

B7~0

DPL1 R/W

00000000 Low byte of 16 bit data pointer 1

85H/DPH1

B7~0

DPH1 R/W

00000000 High byte of 16 bit data pointer 1

86H/DPS

DPS.0 R/W

Pointer 1

Pointer 0

Selection of data pointer, B7~1 are not
used

SMOD

No use. Clear to “o” after power_on reset

SMOD0

No use. Clear to “o” after power_on reset

GF1

General purpose user defined flag

GF0

General purpose user defined flag

Enable

Disable

Power down mode enable bit. Set this bit
to “1” will stop the CPU and oscillation.

87H/PCON

IDL

Enable

Disable

Idle mode enable bit. Set this bit to “1” will
stop the CPU clock, but the oscillator keep
running.

TF1 R/W

Overflow

Timer 1 overflow flag,. TF1 will
automatically clear after INT service
routine.

TR1

Enable

Disable

Timer 1 enable

TF0 R/W

Overflow

Timer 0 overflow flag, TF0 will
automatically clear after INT service
routine

TR0 R/W

Enable

Disable

Timer 0 enable

88H/TCON

IE1

(Bat_fail)

R/W

INT

No INT

Interrupt 1(battery fail INT) flag. Set by
hardware when a pre-selected INT level
(high or low) is detected on INT1. The INT
flag will keep only if the level is held.

Summary of Contents for W928C73

Page 1: ...MCS51 System clock OSC2 76 8 KHz 128 bytes on chip fast RAM 384 bytes on chip MOVX RAM 16K bytes on chip program ROM 32 32 bits on chip flash RAM Timer Two 16 bit timer counters One RTC timer One Watch dog timer One Buzzer timer Four 8 bit bit addressable I O ports Three external interrupt source INT0 INT1 BAT_DET_INT INT3 KEY_INT Battery low detector Battery detector Power fail detector Power dow...

Page 2: ...BS3 P3 1 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG29 SEG28 C O M 2 C O M 1 C O M 0 C O M 3 S E G 35 S E G 34 P 3 2 I N T 0 P 3 3 I N T 1 S E G 0 S E G 1 S E G 2 S E G 3 S E G 4 S E G 5 S E G 6 S E G 7 S E G 8 S E G 9 S E G 10 S E G 11 S E G 12 S E G 13 3 64 LQFP P 0 4 P 0 5 P 0 6 K E Y 2 K E Y 1 K E Y 0 PSEN P 2 4 2 6 P 2 5 P ...

Page 3: ...in Internal pull low PSEN O No connection Test pin P3 0 I O Bit addressable general I O port 3 0 P3 1 I O Bit addressable general I O port 3 1 P3 2 INT0 I O Bit addressable general I O port 3 2 or INT0 defined by SFR P3 3 INT1 I Battery fail interrupt input Connect to V1 5 If voltage potential of battery is less than the 0 8V the INT1 interrupt flag will be set SEG0 O LCD segment signal out SEG1 O...

Page 4: ... O LCD segment signal out P2 2 SEG34 O LCD segment signal out P2 3 SEG35 O LCD segment signal out P2 4 VDD3 I LCD voltage input VDD P2 5 I O I O pin P2 6 I O I O pin P2 7 I O I O pin COM0 O LCD common signal output pins COM1 O LCD common signal output pins COM2 O LCD common signal output pins COM3 O LCD common signal output pins P0 4 I Bit addressable general I O port 0 4 and Key_0 interrupt P0 5 ...

Page 5: ...Instruction Decoder Sequencer Port 4 8 16KB DPTR DPTR 1 PC Address REG Address bus Data bus L_Clock Clock Generator System control I N T E R R U P T Timer 0 Timer 1 Buzzer Timer RTC Timer Watchdog Timer RESET program ROM Power on power low reset XIN2 XOUT2 LCD Driver 32x4 LCD_OFF LCD_ON P0 3 P0 7 P1 5 P1 7 P1 0 P1 2 P3 0 P3 3 P2 5 P2 7 P4 0 4 7 P5 0 5 7 P6 0 6 7 P7 0 7 7 P8 0 8 3 1K FLASH RAM ...

Page 6: ...ions the Program Memory and Data Memory The Program Memory is used to store the instruction op codes while the Data Memory is used for storing data or memory mapped devices The EA pin must connect to high to access on chip program ROM 16 K bytes Program Memory System testing 0000H 0080H 0200H 3FFFH Interrupt vector 0000H 017FH 384 Bytes Data MOVX RAM 00H 7FH Direct indirect Addressing RAM LCD RAM ...

Page 7: ...control When the bit value of the LCD data RAM is 1 the LCD is turned on When the bit value of the LCD data RAM is 0 LCD is turned off The relation between the LCD data RAM and segment common pins is shows below LCD COM3 COM2 COM1 COM0 COM3 COM2 COM1 COM0 Data RAM BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 EEH SEG1 SEG0 EFH SEG3 SEG2 F0H SEG5 SEG4 F1H SEG7 SEG6 F2H SEG9 SEG8 F3H SEG11 SEG10 F...

Page 8: ...High byte of 16 bit data pointer 1 86H DPS B0 DPS 0 R W Pointer 1 Pointer 0 0 Selection of data pointer B7 1 are not used B7 SMOD 0 No use Clear to o after power_on reset B6 SMOD0 0 No use Clear to o after power_on reset B5 0 No use Clear to o after power_on reset B4 0 No use Clear to o after power_on reset B3 GF1 0 General purpose user defined flag B2 GF0 0 General purpose user defined flag B1 PD...

Page 9: ...g control When this bit is set Timer counter x will be enabled if both INTx pin is high and TRx control bit is set When this bit is cleared Timerx is enabled whenever TRx control bit is set Tx_C T timer or counter select When cleared the timer is incremented by internal clocks When set the timer counts high to low edges of the Tx pin M1 M0 Mode 0 0 8 bits with 5 bit pre scalar 0 1 16 bits no pre s...

Page 10: ...ecoder option setup clock output control bit B7 W 0 B6 W 0 B5 W 0 B4 W 0 B3 W 0 B2 W 0 Clear B7 B2 to 0 after power on reset B1 ENBT W Enable Disable 0 Buzzer timer enable used as a general timer 91H PBCON B0 ENBUZ W Enable Disable 0 Buzzer output enable 92H TONE0 B7 0 TONE0 W 00000000 Auto reload value of buzzer timer 96H PLC B7 0 PLC R 00000000 Low byte of program counter 97H PLH B7 0 PLH R 0000...

Page 11: ...4 pins will work as P2 0 2 3 A1H LCDR B0 LCDON W LCD ON LCD OFF 0 LCD driver enable control A2H RTLCD B7 0 RTLCD W 11111111 RTC timer value Set RTLCD 74 for 76 8 KHz crystal B7 EA W Enable Disable 0 Global interrupt enable control B6 ES1 W Enable Disable 0 POCSAG receiving buffer interrupt enable control B5 W 0 Clear this bit to 0 after power on reset B4 W 0 Clear this bit to 0 after power on rese...

Page 12: ...nput B1 P3 1 R W 1 I O P3 1 B0H P3 B0 P3 0 R W 1 I O P3 0 B2 HB B7 0 HB R W 00000000 High byte address of MOVX Ri B7 BTF W High Low 0 Buzzer timer interrupt priority level B6 PS1 W High Low 0 POCSAG receiving buffer interrupt priority level B5 W 0 Clear this bit to 0 after reset B4 W 0 Clear this bit to 0 after reset B3 PT1 W High Low 0 Timer 1 interrupt priority level B2 PX1 W High Low 0 Interrup...

Page 13: ...he bit operations B6 AC R 0 Auxiliary carry Set when the previous operation resulted in a carry during addition or a borrowing during subtraction from the high order nibble B5 F0 R W 0 User define flag B4 RS1 R W 0 B3 RS0 R W 0 RS1 RS0 Register bank selection 0 0 Bank 0 00 07 B0 B7 0 1 Bank 1 08 0F B0 B7 1 0 Bank 2 10 17 B0 B7 1 1 Bank 3 18 1F B0 B7 B2 OV R 0 Overflow flag Set when a carry was gen...

Page 14: ...efore time out will cause an interrupt if EWDI EIE 4 is set and 512 clocks after that a watchdog timer reset will be generated if EWT is set This bit is self clearing B7 P0IO 7 W 0 R W control for P0 7 key3 No use clear this bit to 0 after B6 P0IO 6 W 0 R W control for P0 6 key2 1 input mode without pull high R 0 output mode or input with pull high R Clear this bit after reset for key2 input with ...

Page 15: ...able 0 RTC timer and LCD clock enable B6 EBTI W Enable Disable 0 Buzzer timer interrupt enable B5 ERTI W Enable Disable 0 RTC timer interrupt enable B4 EWDI W Enable Disable 0 Watchdog timer interrupt enable B3 IE3 R 0 External interrupt 3 request flag B2 EX3 W Enable Disable 0 External interrupt 3 enable B1 IE2 R 0 External interrupt 2 request flag B0 EX2 W Enable Disable 0 External interrupt 2 e...

Page 16: ...tween the two by setting or clearing the DPS bit The Data Pointer Select bit DPS is the LSB of the DPS SFR which exists at location 86h Rest bits in this SFR have no effect and are set to 0 When DPS is 0 then DPTR is selected and when set to 1 DPTR1 is selected The user can switch between DPTR and DPTR1 by toggling the DPS bit The quickest way to do this is by the INC instruction The HB register a...

Page 17: ...restored before the hardware reset is applied and frees the oscillator Reset must be held active until the oscillator has restarted and stabilized The wake up operation of W928C73 after power down mode has two approaches wake up using external interrupt INT0 INT1or wake up using RESET For INT0 or INT1 wake up the controller will enter the interrupt service routine and is in the slow operation mode...

Page 18: ...f TMOD selects the function for Timer 1 In addition each Timer can be set to operate in any one of four possible modes The mode selection is done by bits M0 and M1 in the TMOD SFR Mode 0 In Mode 0 the timer act as a 8 bit counter with a 5 bit divide by 32 pre scale In this mode we have a 13 bit timer The 13 bit counter consists of 8 bits of THx and 5 lower bits of TLx The upper 3 bits of TLx are i...

Page 19: ... of either clock cycles clock 4 or pulses on pin Tn System Clock 1 4 TR0 TCON 4 TR1 TCON 6 INT1 P3 3 INT0 P3 2 GATE TMOD 3 GATE TMOD 7 TL0 TL1 TH0 TH1 Interrrpt TF0 TF1 C T TMOD 2 C T TMOD 6 Timer 1 functions are shown in brakets Mode 2 of Timer 0 1 Mode 3 Mode 3 has different operating methods for the two timer For timer 1 mode 3 simply freezes the counter Timer 0 however configures TL0 and TH0 a...

Page 20: ...timer should first be restarted by using RWT This ensures that the timer starts from a known state L_Clock Divider1 Fosc 8192 Fosc 76 8KHz 9 375Hz WD1 0 Selector WDIF RWT WD1 WD0 Interrupt 4 64 Hz 2 34 Hz 1 17 Hz 0 59 Hz 0 29 HZ 0 15 Hz 0 07 Hz 0 04 Hz EWDI 512 clock delay EWT WTRF Reset divider2 WDIF D8 3H EWT D8 1H RWT D8 0H WTRF D8 2H EWDI E8 4H WD1 WD0 8E 7H 8E 6H Buzzer Timer The W928C73 prov...

Page 21: ...h 32 segment output pins and 4 common output pins for a total of 36 4 dots LCDR is used for the LCD driver control The alternating frequency of the LCD can be set as 64 Hz 128 Hz 256 Hz or 512 Hz In addition LCDON LCDR 0 bit can also be used to set up four of the LCD driver output pins segment 0 to segment 31 35 as a I O port For 76 8 KHz and RTLCD 74 The LCD driving potentials are connected to ex...

Page 22: ...sister or output mode Port 0 port 3 are bit addressable The initial state of W928C73 is input mode with pull high resister If LCD is off P48IO is used to control the pull high resister of port 4 port 8 and is byte controllable Interrupt The W928C73 provides 10 interrupt sources with two priority levels The External interrupt 0 has the highest natural priority Software can assign high or low priori...

Page 23: ...as Fig 12 Clearing the SFR DEC_ON P1 2 from high to low after the 192 option bits setting will enable the decoder The BS1 BS2 and BS3 pins will then control the RF to receive POCSAG signal The functions of the option bits are described below DEC_RST P1 3 DEC_TXCLK P1 0 Total 192 clock At least 2 mS At least 2 mS DEC_TXDATA P1 1 D0 D1 D2 D3 D4 D5 D192 At least 1 s µ DEC_ON P1 2 BS1 BS2 BS3 ...

Page 24: ...DC8 D108 ADD8 D140 ADE8 D172 ADF8 D13 ADA7 D45 ADB7 D77 ADC7 D109 ADD7 D141 ADE7 D173 ADF7 D14 ADA6 D46 ADB6 D78 ADC6 D110 ADD6 D142 ADE6 D174 ADF6 D15 ADA5 D47 ADB5 D79 ADC5 D111 ADD5 D143 ADE5 D175 ADF5 D16 ADA4 D48 ADB4 D80 ADC4 D112 ADD4 D144 ADE4 D176 ADF4 D17 ADA3 D49 ADB3 D81 ADC3 D113 ADD3 D145 ADE3 D177 ADF3 D18 ADA2 D50 ADB2 D82 ADC2 D114 ADD2 D146 ADE2 D178 ADF2 D19 ADA1 D51 ADB1 D83 AD...

Page 25: ...ncorrectable codeword 0 0 Reception termination on two consecutive uncorrectable codeword 0 1 Reserved 1 0 Reserved 1 1 FUNCTION OPTION NRZ Signal Input Shmt Without Schmitt Trigger 0 With Schmitt Trigger 1 FUNCTION OPTION Out of range hold time when synchronization lost OUTR1 OUTR2 512 bps 1200 2400 bps 36 sec 31 sec 0 0 72 sec 61 sec 0 1 144 sec 123 sec 1 0 288 sec 246 sec 1 1 FUNCTION OPTION Ba...

Page 26: ...90 mS 1 67 mS 0 0 11 71 mS 5 00 mS 0 1 19 53 mS 8 33 mS 1 0 27 34 mS 11 67 mS 1 1 FUNCTION OPTION TBS3 PL4 PL3 512 bps 1200 2400 bps 0 00 mS 0 00 mS 0 0 31 25 mS 13 33 mS 0 1 62 50 mS 26 67 mS 1 0 93 75 mS 40 00 mS 1 1 FUNCTION OPTION Preamble length PREL1 PREL0 512 bit 0 0 896 bit 0 1 1024 bit 1 0 1792 bit 1 1 ...

Page 27: ...word followed by message words and ended with the termination word If another addressed matched message is received right after the first message the second address word will come out followed by the previous termination word as shown below The detail formats of address word message word and termination word are as following ADR MSG A1 MSG AN TRM A ADR B SINT SBUF3 1 Address A POCSAG Signal Data A...

Page 28: ...4 SB2 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 M13 M12 M11 M10 M9 M8 M7 M6 SB1 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 M5 M4 M3 M2 SYNC ER0 TM 0 CM 1 Note SYNC sync detection 1 syncloss 0 catch sync ER0 error condition after correction 1 error 0 No error Termination Word Format SB3 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 0 0 0 0 0 0 0 0 SB2 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT ...

Page 29: ... 32 frame 32 bit flash ROM cell typically used to store the POCSAG addresses and parameters The single voltage supply eliminates the need for an extra pump circuit during programming and erasing There are 3 different operation mode read program and erase The different mode is determined by the number of the clocks of the CTRL bit while the SFR MODE is set to high The programming timing is shown be...

Page 30: ...e flash ROM This flash ROM is programmed on a frame basis Each frame contains 32 bits of data The LSB of data is shift in first The programming time Tpr must be more than 400 µS Each programming pulse will increase the frame address by 1 Erase Mode This mode will erase all the data in the flash ROM The typical whole chip erase time should be larger than 50 mS Twe TIMING WAVEFORMS Flash ROM Program...

Page 31: ... the DATA should be latched in the CLK falling edge 2 read mode the DATA should be latched in before CLK low 3 when in the read mode must let P0IO 0 and P0 0 DATA set 1 input mode 4 set GF1 general flag to 1 will enable 1K flash DC CHARACTERISTICS VDD 3V VSS 0V TA 25 C PARAMETER SYM CONDITIONS LIMITS UNIT MIN TYP MAX Operating Voltage VDD 2 4 3 6 V Flash ROM Operating Voltage VFLASH 2 5 3 6 V Norm...

Page 32: ...DDR CTRL TGCA Page coding mode 1 µS Interval Between Addressing End Block erase Begin TAE Block erase mode 1 µS Interval Between MODE Rising Edge CTRL Clock Begin TMB Mode selection 500 nS Interval Between CTRL Clock End MODE Falling Edge TME Mode selection 500 nS Interval Between MODE Falling Edge Another Pin Active TGM 1 µS Data Access Time TRA Read mode 500 nS Data Set up Time TWS Write mode 25...

Page 33: ... 1 5 P V S E G 0 S E G 1 S E G 2 S E G 3 S E G 4 S E G 5 S E G 6 S E G 7 S E G 8 S E G 9 S E G 10 S E G 11 S E G 12 S E G 13 V 2 7 P V D D X O U T 2 X I N 2 3 P1 5 P1 6 P1 7 Vss RESET EA TEST1 NC TEST2 NC P3 0 PSEN NC BL_RF DI BS1 BS2 BS3 P3 1 V V Key2 Key1 Key0 From RF bat_det Signal_in RFEN QC PLEN V 76 8K PLL EP_3 Battery detector SEG28 SEG29 W928C73 64 LQFP P 2 6 P 2 5 P 2 4 10 PF C O M C O M ...

Page 34: ...134 U S A TEL 408 9436666 FAX 408 5441798 Note All data and specifications are subject to change withou t notice Headquarters No 4 Creation Rd III Science Based Industrial Park Hsinchu Taiwan TEL 886 3 5770066 FAX 886 3 5792766 http www winbond com tw Voice Fax on demand 886 2 27197006 Taipei Office 11F No 115 Sec 3 Min Sheng East Rd Taipei Taiwan TEL 886 2 27190505 FAX 886 2 27197502 Winbond Elec...

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