WECA W6810DK
2727 N First Street, San Jose CA 95134
6
Frame Sync = 4 BCLK
Frame Sync = 3 BCLK
ON
ON
OFF
OFF
Long Frame Sync
Short Frame Sync
8
1
ON
OFF
8
1
Frame Sync = 1
Frame Sync = 2
ON
OFF
BIT CLOCK:
Bit clock is routed to the 2x20 (J11) header connector pins 5 (BCLKT) and 36 (BCLKR)
through J17A and J14. J1 is used to select the frequency at which Bit Clock operates. The
selected frequencies are 4.096 MHz, 2.048 MHz, 1.024 MHz, 512KHz, 128KHz and
64KHz.
256 KHZ:
The 256 KHz is a possible frequency setting for the master clock (MCLK) J15A(SW4)
input on the chosen PCM Codec-filter. J15B will configure the MCLK input to have a
frequency equal to Bit Clock.
