Winbond Spiflash W25Q80BV Manual Download Page 37

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W25Q80BV

Publication Release Date: Augest 01, 2012

- 37 - Revision G

M7-0

/CS

CLK

Mode 0

Mode 3

A23-16

A15-8

A7-0

Byte 1

Byte 2

IOs switch from
Input to Output

Byte 3

Byte 4

Figure 16b. Octal Word Read Quad I/O Instruction Sequence (Previous instruction set M5-4 = 10)

Summary of Contents for Spiflash W25Q80BV

Page 1: ...W25Q80BV Publication Release Date Augest 01 2012 1 Revision G 8M BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI ...

Page 2: ...Serial Clock CLK 9 5 BLOCK DIAGRAM 10 6 FUNCTIONAL DESCRIPTION 11 6 1 SPI OPERATIONS 11 6 1 1 Standard SPI Instructions 11 6 1 2 Dual SPI Instructions 11 6 1 3 Quad SPI Instructions 11 6 1 4 Hold Function 11 6 2 WRITE PROTECTION 12 6 2 1 Write Protect Features 12 7 CONTROL AND STATUS REGISTERS 13 7 1 STATUS REGISTER 13 7 1 1 BUSY 13 7 1 2 Write Enable Latch WEL 13 7 1 3 Block Protect Bits BP2 BP1 ...

Page 3: ...ad Quad I O EBh 32 7 2 16 Word Read Quad I O E7h 34 7 2 17 Octal Word Read Quad I O E3h 36 7 2 18 Set Burst with Wrap 77h 38 7 2 19 Continuous Read Mode Bits M7 0 39 7 2 20 Continuous Read Mode Reset FFh or FFFFh 39 7 2 21 Page Program 02h 40 7 2 22 Quad Input Page Program 32h 41 7 2 23 Sector Erase 20h 42 7 2 24 32KB Block Erase 52h 43 7 2 25 64KB Block Erase D8h 44 7 2 26 Chip Erase C7h 60h 45 7...

Page 4: ... WP Timing 66 9 PACKAGE SPECIFICATION 67 9 1 8 Pin SOIC 150 mil Package Code SN 67 9 2 8 Pin VSOP 150 mil Package Code SV 68 9 3 8 Pin SOIC 208 mil Package Code SS 69 9 4 8 Pin VSOP 208 mil Package Code ST 70 9 5 8 Pin PDIP 300 mil Package Code DA 71 9 6 8 Pad WSON 6x5mm Package Code ZP 72 9 7 8 Pad USON 2x3 mm Package Code UX 74 9 8 24 Ball TFBGA 8x6 mm Package Code TB 5x5 1 ball array 75 9 9 24 ...

Page 5: ...operation A Hold pin Write Protect pin and programmable write protection with top bottom or complement array control provide further control flexibility Additionally the device supports JEDEC standard manufacturer and device identification with a 64 bit Unique Serial Number 2 FEATURES Family of SpiFlash Memories W25Q80BV 8M bit 1M byte 1 048 576 256 byte per programmable page Standard SPI CLK CS D...

Page 6: ... 8x6 mm TFBGA 5x5 ball array package code TB 6x4 ball array package code TC as shown in Figure 1a d respectively Package diagrams and dimensions are illustrated at the end of this datasheet 3 1 Pin Configuration SOIC VSOP 150 208 mil 1 2 3 4 8 7 6 5 CS DO IO1 WP IO2 GND VCC HOLD IO3 DI IO0 CLK Top View Figure 1a W25Q80BV Pin Assignments 8 pin SOIC VSOP 150 208 mil Package Code SN SS SV ST 3 2 Pad ...

Page 7: ... SOIC VSOP WSON USON PDIP 300 mil PIN NO PIN NAME I O FUNCTION 1 CS I Chip Select Input 2 DO IO1 I O Data Output Data Input Output 1 1 3 WP IO2 I O Write Protect Input Data Input Output 2 2 4 GND Ground 5 DI IO0 I O Data Input Data Input Output 0 1 6 CLK I Serial Clock Input 7 HOLD IO3 I O Hold Input Data Input Output 3 2 8 VCC Power Supply 1 IO0 and IO1 are used for Standard and Dual SPI instruct...

Page 8: ...e Code TB C5 NC D5 NC E5 NC A5 NC Figure 1d W25Q80BV Ball Assignments 24 ball TFBGA 8x6 mm Package Code TB or TC 3 6 Ball Description TFBGA 8x6 mm BALL NO PIN NAME I O FUNCTION B2 CLK I Serial Clock Input B3 GND Ground B4 VCC Power Supply C2 CS I Chip Select Input C4 WP IO2 I O Write Protect Input Data Input Output 2 2 D2 DO IO1 I O Data Output Data Input Output 1 1 D3 DI IO0 I O Data Input Data I...

Page 9: ... instructions addresses or data to the device on the rising edge of CLK and read data or status from the device on the falling edge of CLK Quad SPI instructions require the non volatile Quad Enable bit QE in Status Register 2 to be set When QE 1 the WP pin becomes IO2 and HOLD pin becomes IO3 4 3 Write Protect WP The Write Protect WP pin can be used to prevent the Status Register from being writte...

Page 10: ...0FFh 07FF00h 07FFFFh Block 7 64KB 070000h 0700FFh 08FF00h 08FFFFh Block 8 64KB 080000h 0800FFh 0FFF00h 0FFFFFh Block 15 64KB 0F0000h 0F00FFh 003000h 0030FFh 002000h 0020FFh 001000h 0010FFh Column Decode And 256 Byte Page Buffer Beginning Page Address Ending Page Address W25Q80BV SPI Command Control Logic Byte Address Latch Counter Status Register Write Control Logic Page Address Latch Counter DO I...

Page 11: ...n using the Fast Read Quad Output 6Bh Fast Read Quad I O EBh Word Read Quad I O E7h and Octal Word Read Quad I O E3h instructions These instructions allow data to be transferred to or from the device six to eight times the rate of ordinary Serial Flash The Quad Read instructions offer a significant improvement in continuous and random access transfer rates allowing fast code shadowing to RAM or ex...

Page 12: ...ns are recognized During power up and after the VCC voltage exceeds VWI all program and erase related instructions are further disabled for a time delay of tPUW This includes the Write Enable Page Program Sector Erase Block Erase Chip Erase and the Write Status Register instructions Note that the chip select pin CS must track the VCC supply level at power up until the VCC min level and tVSL time d...

Page 13: ... read only bit in the status register S1 that is set to 1 after executing a Write Enable Instruction The WEL status bit is cleared to 0 when the device is write disabled A write disable state occurs upon power up or after any of the following instructions Write Disable Page Program Quad Page Program Sector Erase Block Erase Chip Erase Write Status Register Erase Security Register and Program Secur...

Page 14: ... locked and can not be written to 0 1 1 Hardware Unprotected When WP pin is high the Status register is unlocked and can be written to after a Write Enable instruction WEL 1 1 0 X Power Supply Lock Down Status Register is protected and can not be written to again until the next power down power up cycle 1 1 1 X One Time Program 2 Status Register is permanently protected and can not be written to N...

Page 15: ...T non volatile TOP BOTTOM PROTECT non volatile BLOCK PROTECT BITS non volatile WRITE ENABLE LATCH ERASE WRITE IN PROGRESS S7 S6 S5 S4 S3 S2 S1 S0 SRP0 SEC TB BP2 BP1 BP0 WEL BUSY STATUS REGISTER PROTECT 0 non volatile SECTOR PROTECT non volatile TOP BOTTOM PROTECT non volatile BLOCK PROTECT BITS non volatile WRITE ENABLE LATCH ERASE WRITE IN PROGRESS Figure 3a Status Register 1 S15 S14 S13 S12 S11...

Page 16: ...er 1 4 0 1 1 0 0 0 thru 7 000000h 07FFFFh 512KB Lower 1 2 0 X 1 0 1 0 thru 15 000000h 0FFFFFh 1MB ALL X X 1 1 1 0 thru 15 000000h 0FFFFFh 1MB ALL 1 0 0 0 1 15 0FF000h 0FFFFFh 4KB Upper 1 256 1 0 0 1 0 15 0FE000h 0FFFFFh 8KB Upper 1 128 1 0 0 1 1 15 0FC000h 0FFFFFh 16KB Upper 1 64 1 0 1 0 1 15 0F8000h 0FFFFFh 32KB Upper 1 32 1 0 1 X 0 15 0F8000h 0FFFFFh 32KB Upper 1 32 1 1 0 0 1 0 000000h 000FFFh 4...

Page 17: ...FFFh 768KB Upper 3 4 0 1 1 0 0 8 thru 15 080000h 0FFFFFh 512KB Upper 1 2 X X 1 1 1 NONE NONE NONE NONE 1 0 0 0 1 0 thru 15 000000h 0FEFFFh 1 020KB Lower 255 256 1 0 0 1 0 0 thru 15 000000h 0FDFFFh 1 016KB Lower 127 128 1 0 0 1 1 0 thru 15 000000h 0FBFFFh 1 008KB Lower 63 64 1 0 1 0 X 0 thru 15 000000h 0F7FFFh 992KB Lower 31 32 1 0 1 1 0 0 thru 15 000000h 0F7FFFh 992KB Lower 31 32 1 1 0 0 1 0 thru ...

Page 18: ...d with the rising edge of edge CS Clock relative timing diagrams for each instruction are included in figures 4 through 37 All read instructions can be completed after any clocked bit However all instructions that Write Program or Erase must complete on a byte boundary CS driven high after a full 8 bits have been clocked otherwise the instruction will be ignored This feature further protects the d...

Page 19: ...B 20h A23 A16 A15 A8 A7 A0 Block Erase 32KB 52h A23 A16 A15 A8 A7 A0 Block Erase 64KB D8h A23 A16 A15 A8 A7 A0 Chip Erase C7h 60h Erase Program Suspend 75h Erase Program Resume 7Ah Power down B9h Continuous Read Mode Reset 4 FFh FFh Notes 1 Data bytes are shifted with Most Significant Bit first Byte fields with data in parenthesis indicate data being read from the device on the DO pin 2 The Status...

Page 20: ...xx W6 W4 4 Notes 1 Dual Output data IO0 D6 D4 D2 D0 IO1 D7 D5 D3 D1 2 Dual Input Address IO0 A22 A20 A18 A16 A14 A12 A10 A8 A6 A4 A2 A0 M6 M4 M2 M0 IO1 A23 A21 A19 A17 A15 A13 A11 A9 A7 A5 A3 A1 M7 M5 M3 M1 3 Quad Output Data IO0 D4 D0 IO1 D5 D1 IO2 D6 D2 IO3 D7 D3 4 Quad Input Address Set Burst with Wrap Input IO0 A20 A16 A12 A8 A4 A0 M4 M0 IO0 x x x x x x W4 x IO1 A21 A17 A13 A9 A5 A1 M5 M1 IO1 ...

Page 21: ...cturer ID15 ID8 Memory Type ID7 ID0 Capacity Read Unique ID 4Bh dummy dummy dummy dummy ID63 ID0 Read SFDP Register 5Ah 00h 00h A7 A0 dummy D7 0 Erase Security Registers 3 44h A23 A16 A15 A8 A7 A0 Program Security Registers 3 42h A23 A16 A15 A8 A7 A0 D7 D0 D7 D0 Read Security Registers 3 48h A23 A16 A15 A8 A7 A0 dummy D7 0 Notes 1 The Device ID will repeat continuously until CS terminates the inst...

Page 22: ...tile Status Register bits described in section 7 1 can also be written to as volatile bits This gives more flexibility to change the system configuration and memory protection schemes quickly without waiting for the typical non volatile bit write cycles or affecting the endurance of the Status Register non volatile bits To write the volatile values into the Status Register bits the Write Enable fo...

Page 23: ...then driving CS high Note that the WEL bit is automatically reset after Power up and upon completion of the Write Status Register Erase Program Security Registers Page Program Quad Page Program Sector Erase Block Erase and Chip Erase instructions Write Disable instruction can also be used to invalidate the Write Enable for Volatile Status Register instruction CS CLK DI IO0 DO IO1 Mode 0 Mode 3 0 1...

Page 24: ...Figure 7 Read Status Register Instruction Sequence Diagram 7 2 9 Write Status Register 01h The Write Status Register instruction allows the Status Register to be written Only non volatile Status Register bits SRP0 SEC TB BP2 BP1 BP0 bits 7 thru 2 of Status Register 1 and CMP LB3 LB2 LB1 QE SRP1 bits 14 thru 8 of Status Register 2 can be written to All other Status Register bit locations are read o...

Page 25: ...it The BUSY bit is a 1 during the Write Status Register cycle and a 0 when the cycle is finished and ready to accept other instructions again After the Write Status Register cycle has finished the Write Enable Latch WEL bit in the Status Register will be cleared to 0 During volatile Status Register write operation 50h combined with 01h after CS is driven high the Status Register bits will be refre...

Page 26: ...ach byte of data is shifted out allowing for a continuous stream of data This means that the entire memory can be accessed with a single instruction as long as the clock continues The instruction is completed by driving CS high The Read Data instruction sequence is shown in figure 9 If a Read Data instruction is issued while an Erase Program or Write cycle is in process BUSY 1 the instruction is i...

Page 27: ...e 10 The dummy clocks allow the devices internal circuits additional time for setting up the initial address During the dummy clocks the data value on the DO pin is a don t care CS CLK DI IO0 DO IO1 Mode 0 Mode 3 0 1 2 3 4 5 6 7 Instruction 0Bh High Impedance 8 9 10 28 29 30 31 24 Bit Address 23 22 21 3 2 1 0 Data Out 1 CS CLK DI IO0 DO IO1 32 33 34 35 36 37 38 39 Dummy Clocks High Impedance 40 41...

Page 28: ...This is accomplished by adding eight dummy clocks after the 24 bit address as shown in figure 11 The dummy clocks allow the device s internal circuits additional time for setting up the initial address The input data during the dummy clocks is don t care However the IO0 pin should be high impedance prior to the falling edge of the first data out clock CS CLK DI IO0 DO IO1 Mode 0 Mode 3 0 1 2 3 4 5...

Page 29: ...eristics This is accomplished by adding eight dummy clocks after the 24 bit address as shown in figure 12 The dummy clocks allow the device s internal circuits additional time for setting up the initial address The input data during the dummy clocks is don t care However the IO pins should be high impedance prior to the falling edge of the first data out clock CS CLK Mode 0 Mode 3 0 1 2 3 4 5 6 7 ...

Page 30: ...ntinuous Read Mode bits M5 4 1 0 then the next Fast Read Dual I O instruction after CS is raised and then lowered does not require the BBh instruction code as shown in figure 13b This reduces the instruction sequence by eight clocks and allows the Read address to be immediately entered after CS is asserted low If the Continuous Read Mode bits M5 4 do not equal to 1 0 the next instruction after CS ...

Page 31: ...DO IO1 0 7 5 3 1 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 IOs switch from Input to Output 6 7 22 20 18 16 23 21 19 17 14 12 10 8 15 13 11 9 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 11 15 1 A23 16 A15 8 A7 0 M7 0 Byte 1 Byte 2 Byte 3 Byte 4 0 1 2 3 4 5 6 7 16 17 18 20 21 22 19 23 MSB Figure 13b Fast Read Dual I O Instruction Sequence Previous instruction set M5 4 10 ...

Page 32: ... However the IO pins should be high impedance prior to the falling edge of the first data out clock If the Continuous Read Mode bits M5 4 1 0 then the next Fast Read Quad I O instruction after CS is raised and then lowered does not require the EBh instruction code as shown in figure 14b This reduces the instruction sequence by eight clocks and allows the Read address to be immediately entered afte...

Page 33: ...und feature for the following EBh commands When Wrap Around is enabled the data being accessed can be limited to either a 8 16 32 or 64 byte section of a 256 byte page The output data starts at the initial address specified in the instruction once it reaches the ending boundary of the 8 16 32 64 byte section the output will wrap around to the beginning boundary automatically until CS is pulled hig...

Page 34: ...IO pins should be high impedance prior to the falling edge of the first data out clock If the Continuous Read Mode bits M5 4 1 0 then the next Fast Read Quad I O instruction after CS is raised and then lowered does not require the E7h instruction code as shown in figure 15b This reduces the instruction sequence by eight clocks and allows the Read address to be immediately entered after CS is asser...

Page 35: ...ature for the following E7h commands When Wrap Around is enabled the data being accessed can be limited to either a 8 16 32 or 64 byte section of a 256 byte page The output data starts at the initial address specified in the instruction once it reaches the ending boundary of the 8 16 32 64 byte section the output will wrap around to the beginning boundary automatically until CS is pulled high to t...

Page 36: ...ould be high impedance prior to the falling edge of the first data out clock If the Continuous Read Mode bits M5 4 1 0 then the next Fast Read Quad I O instruction after CS is raised and then lowered does not require the E3h instruction code as shown in figure 16b This reduces the instruction sequence by eight clocks and allows the Read address to be immediately entered after CS is asserted low If...

Page 37: ...0 16 12 8 21 17 22 18 23 19 13 9 14 10 15 11 A23 16 6 7 4 0 5 1 6 2 7 3 A15 8 A7 0 4 0 5 1 6 2 7 3 Byte 1 Byte 2 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 5 6 7 IOs switch from Input to Output Byte 3 8 9 10 11 12 13 4 0 5 1 6 2 7 3 Byte 4 Figure 16b Octal Word Read Quad I O Instruction Sequence Previous instruction set M5 4 10 ...

Page 38: ...0 1 Yes 16 byte No N A 1 0 Yes 32 byte No N A 1 1 Yes 64 byte No N A Once W6 4 is set by a Set Burst with Wrap instruction all the following Fast Read Quad I O and Word Read Quad I O instructions will use the W6 4 setting to access the 8 16 32 64 byte section within any page To exit the Wrap Around function and return to normal read operation another Set Burst with Wrap instruction should be issue...

Page 39: ...ad Mode Reset FFh or FFFFh Continuous Read Mode Reset instruction can be used to set M4 1 thus the device will release the Continuous Read Mode and return to normal SPI operation as shown in figure 18 CS CLK Mode 0 Mode 3 0 1 IO0 IO1 IO2 IO3 2 3 4 5 Don t Care 6 7 8 9 10 11 12 13 14 15 Mode Bit Reset for Quad I O FFh Mode 0 Mode 3 Mode Bit Reset for Dual I O FFFFh Don t Care Don t Care Figure 18 C...

Page 40: ...to the device the addressing will wrap to the beginning of the page and overwrite previously sent data As with the write and erase instructions the CS pin must be driven high after the eighth bit of the last byte has been latched If this is not done the Page Program instruction will not be executed After CS is driven high the self timed Page Program instruction will commence for a time duration of...

Page 41: ...Quad Page Program instruction Status Register 1 WEL 1 The instruction is initiated by driving the CS pin low then shifting the instruction code 32h followed by a 24 bit address A23 A0 and at least one data byte into the IO pins The CS pin must be held low for the entire length of the instruction while data is being sent to the device All other functions of Quad Page Program are identical to standa...

Page 42: ... self timed Sector Erase instruction will commence for a time duration of tSE See AC Characteristics While the Sector Erase cycle is in progress the Read Status Register instruction may still be accessed for checking the status of the BUSY bit The BUSY bit is a 1 during the Sector Erase cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions again Afte...

Page 43: ...ter CS is driven high the self timed Block Erase instruction will commence for a time duration of tBE1 See AC Characteristics While the Block Erase cycle is in progress the Read Status Register instruction may still be accessed for checking the status of the BUSY bit The BUSY bit is a 1 during the Block Erase cycle and becomes a 0 when the cycle is finished and the device is ready to accept other ...

Page 44: ... self timed Block Erase instruction will commence for a time duration of tBE See AC Characteristics While the Block Erase cycle is in progress the Read Status Register instruction may still be accessed for checking the status of the BUSY bit The BUSY bit is a 1 during the Block Erase cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions again After t...

Page 45: ... CS is driven high the self timed Chip Erase instruction will commence for a time duration of tCE See AC Characteristics While the Chip Erase cycle is in progress the Read Status Register instruction may still be accessed to check the status of the BUSY bit The BUSY bit is a 1 during the Chip Erase cycle and becomes a 0 when finished and the device is ready to accept other instructions again After...

Page 46: ... going If the SUS bit equals to 1 or the BUSY bit equals to 0 the Suspend instruction will be ignored by the device A maximum of time of tSUS See AC Characteristics is required to suspend the erase or program operation The BUSY bit in the Status Register will be cleared from 1 to 0 within tSUS and the SUS bit in the Status Register will be set from 0 to 1 immediately after Erase Program Suspend Fo...

Page 47: ...ector or Block will complete the erase operation or the page will complete the program operation If the SUS bit equals to 0 or the BUSY bit equals to 1 the Resume instruction 7Ah will be ignored by the device The Erase Program Resume instruction sequence is shown in figure 26 Resume instruction is ignored if the previous Erase Program Suspend operation was interrupted by unexpected power off It is...

Page 48: ...cuted After CS is driven high the power down state will entered within the time duration of tDP See AC Characteristics While in the power down state only the Release from Power down Device ID instruction which restores the device to normal operation will be recognized All other instructions are ignored This includes the Read Status Register instruction which is always available during normal opera...

Page 49: ...wed by 3 dummy bytes The Device ID bits are then shifted out on the falling edge of CLK with most significant bit MSB first as shown in figure 28a The Device ID values for the W25Q80BV is listed in Manufacturer and Device Identification table The Device ID can be read continuously The instruction is completed by driving CS high When used to release the device from the power down state and obtain t...

Page 50: ...0 1 2 3 4 5 6 7 Instruction ABh High Impedance 8 9 29 30 31 3 Dummy Bytes 23 22 2 1 0 Mode 0 Mode 3 7 6 5 4 3 2 1 0 32 33 34 35 36 37 38 Device ID Power down current Stand by current MSB Figure 28b Release Power down Device ID Instruction Sequence Diagram ...

Page 51: ...EFh and the Device ID are shifted out on the falling edge of CLK with most significant bit MSB first as shown in figure 29 The Device ID values for the W25Q80BV is listed in Manufacturer and Device Identification table If the 24 bit address is initially set to 000001h the Device ID will be read first and then followed by the Manufacturer ID The Manufacturer and Device IDs can be read continuously ...

Page 52: ...re 30 The Device ID values for the W25Q80BV is listed in Manufacturer and Device Identification table If the 24 bit address is initially set to 000001h the Device ID will be read first and then followed by the Manufacturer ID The Manufacturer and Device IDs can be read continuously alternating from one to the other The instruction is completed by driving CS high CS CLK DI IO0 DO IO1 Mode 0 Mode 3 ...

Page 53: ...figure 31 The Device ID values for the W25Q80BV is listed in Manufacturer and Device Identification table If the 24 bit address is initially set to 000001h the Device ID will be read first and then followed by the Manufacturer ID The Manufacturer and Device IDs can be read continuously alternating from one to the other The instruction is completed by driving CS high Mode 0 Mode 3 0 1 2 3 4 5 6 7 I...

Page 54: ...fting the instruction code 4Bh followed by a four bytes of dummy clocks After which the 64 bit ID is shifted out on the falling edge of CLK as shown in figure 32 CS CLK DI IO0 DO IO1 Mode 0 Mode 3 0 1 2 3 4 5 6 7 Instruction 4Bh High Impedance 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CS CLK DI IO0 DO IO1 24 25 26 27 28 29 30 31 32 33 34 36 37 38 35 23 Mode 0 Mode 3 Dummy Byte 1 Dummy Byte 2 3...

Page 55: ...e JEDEC assigned Manufacturer ID byte for Winbond EFh and two Device ID bytes Memory Type ID15 ID8 and Capacity ID7 ID0 are then shifted out on the falling edge of CLK with most significant bit MSB first as shown in figure 33 For memory type and capacity values refer to Manufacturer and Device Identification table CS CLK DI IO0 DO IO1 Mode 0 Mode 3 0 1 2 3 4 5 6 7 Instruction 9Fh High Impedance 8 ...

Page 56: ...initiated by driving the CS pin low and shifting the instruction code 5Ah followed by a 24 bit address A23 A0 1 into the DI pin Eight dummy clocks are also required before the SFDP register contents are shifted out on the falling edge of the 40th CLK with most significant bit MSB first as shown in figure 34 For SFDP register values and descriptions please refer to the Winbond Application Note for ...

Page 57: ...35 The CS pin must be driven high after the eighth bit of the last byte has been latched If this is not done the instruction will not be executed After CS is driven high the self timed Erase Security Register operation will commence for a time duration of tSE See AC Characteristics While the Erase Security Register cycle is in progress the Read Status Register instruction may still be accessed for...

Page 58: ... 0 0 0 Byte Address Security Register 2 00h 0 0 1 0 0 0 0 0 Byte Address Security Register 3 00h 0 0 1 1 0 0 0 0 Byte Address The Program Security Register instruction sequence is shown in figure 36 The Security Register Lock Bits LB 3 1 in the Status Register 2 can be used to OTP protect the security registers Once a lock bit is set to 1 the corresponding security register will be permanently loc...

Page 59: ...will reset to 00h the first byte of the register and continue to increment The instruction is completed by driving CS high The Read Security Register instruction sequence is shown in figure 37 If a Read Security Register instruction is issued while an Erase Program or Write cycle is in process BUSY 1 the instruction is ignored and will not have any effects on the current cycle The Read Security Re...

Page 60: ...hese levels is not guaranteed Exposure to absolute maximum ratings may affect device reliability Exposure beyond absolute maximum ratings may cause permanent damage 2 Compliant with JEDEC Standard J STD 20C for small body Sn Pb or Pb free Green assembly and the European directive on restrictions on hazardous substances RoHS 2002 95 EU 3 JEDEC Std JESD22 A114A C1 100pF R1 1500 ohms R2 500 ohms 8 2 ...

Page 61: ...efore Write Instruction tPUW 1 5 ms Write Inhibit Threshold Voltage VWI 1 1 0 2 0 V Note 1 These parameters are characterized only VCC tVSL Read Instructions Allowed Device is fully Accessible tPUW CS must track VCC Program Erase and Write Instructions are ignored Reset State VCC max VCC min VWI Time Figure 38a Power up Timing and Voltage Levels Figure 38b Power up Power Down Requirement ...

Page 62: ... 7 8 9 10 5 12 mA Current Read Data Dual Quad 50MHz 2 ICC3 C 0 1 VCC 0 9 VCC DO Open 7 8 9 10 12 13 5 mA Current Read Data Dual Output Read Quad Output Read 80MHz 2 ICC3 C 0 1 VCC 0 9 VCC DO Open 10 11 12 15 16 5 18 mA Current Write Status Register ICC4 CS VCC 8 12 mA Current Page Program ICC5 CS VCC 20 25 mA Current Sector Block Erase ICC6 CS VCC 20 25 mA Current Chip Erase ICC7 CS VCC 20 25 mA I...

Page 63: ...ll Times TR TF 5 ns Input Pulse Voltages VIN 0 2 VCC to 0 8 VCC V Input Timing Reference Voltages IN 0 3 VCC to 0 7 VCC V Output Timing Reference Voltages OUT 0 5 VCC to 0 5 VCC V Note 1 Output Hi Z is defined as the point where data out is no longer driven Input and Output Timing Reference Levels Input Levels 0 8 VCC 0 2 VCC 0 5 VCC Figure 39 AC Measurement I O Waveform ...

Page 64: ... to peak tCHCL 2 0 1 V ns CS Active Setup Time relative to CLK tSLCH tCSS 5 ns CS Not Active Hold Time relative to CLK tCHSL 5 ns Data In Setup Time tDVCH tDSU 2 ns Data In Hold Time tCHDX tDH 5 ns CS Active Hold Time relative to CLK tCHSH 5 ns CS Not Active Setup Time relative to CLK tSHCH 5 ns CS Deselect Time for Array Read Array Read tSHSL1 tCSH 10 ns CS Deselect Time for Erase or Program Read...

Page 65: ...ure Read tRES2 2 1 8 µs CS High to next Instruction after Suspend tSUS 2 20 µs Write Status Register Time tW 10 15 ms Byte Program Time First Byte 4 tBP1 30 50 µs Additional Byte Program Time After First Byte 4 tBP2 2 5 12 µs Page Program Time tPP 0 7 3 ms Sector Erase Time 4KB tSE 30 200 400 5 ms Block Erase Time 32KB tBE1 120 800 ms Block Erase Time 64KB tBE2 150 1 000 ms Chip Erase Time tCE 2 6...

Page 66: ...T 8 9 Serial Input Timing CS CLK IO input tCHSL MSB IN tSLCH tDVCH tCHDX tSHCH tCHSH tCLCH tCHCL LSB IN tSHSL 8 10 HOLD Timing CS CLK IO output HOLD tCHHL tHLCH tCHHH tHHCH tHLQZ tHHQX IO input 8 11 WP Timing CS CLK WP tWHSL tSHWL IO input Write Status Register is allowed Write Status Register is not allowed ...

Page 67: ... 0 10 0 25 0 004 0 010 b 0 33 0 51 0 013 0 020 c 0 19 0 25 0 008 0 010 E 3 3 80 4 00 0 150 0 157 D 3 4 80 5 00 0 188 0 196 e 2 1 27 BSC 0 050 BSC HE 5 80 6 20 0 228 0 244 Y 4 0 10 0 004 L 0 40 1 27 0 016 0 050 θ 0 10 0 10 Notes 1 Controlling dimensions millimeters unless otherwise specified 2 BSC Basic lead spacing between centers 3 Dimensions D and E do not include mold flash protrusions and shou...

Page 68: ...0 005 BSC D 4 80 4 90 5 00 0 189 0 193 0 197 E 5 80 6 00 6 20 0 228 0 236 0 244 E1 3 80 3 90 4 00 0 150 0 154 0 157 e 1 27 BSC 0 050 BSC L 0 40 0 71 1 27 0 016 0 028 0 050 θ 0 10 0 10 Notes 1 Dimension D does not include mold flash protrusions or gate burrs Mold flash protrusions and gate burrs shall not exceed 0 15mm per side 2 Dimension E1 does not include inter lead flash or protrusions Inter l...

Page 69: ...8 5 28 5 38 0 204 0 208 0 212 D1 5 13 5 23 5 33 0 202 0 206 0 210 E 5 18 5 28 5 38 0 204 0 208 0 212 E1 5 13 5 23 5 33 0 202 0 206 0 210 e 2 1 27 BSC 0 050 BSC H 7 70 7 90 8 10 0 303 0 311 0 319 L 0 50 0 65 0 80 0 020 0 026 0 031 y 0 10 0 004 θ 0 8 0 8 Notes 1 Controlling dimensions millimeters unless otherwise specified 2 BSC Basic lead spacing between centers 3 Dimensions D1 and E1 do not includ...

Page 70: ... 0 039 A1 0 05 0 10 0 15 0 002 0 004 0 006 A2 0 75 0 80 0 85 0 030 0 031 0 033 b 0 35 0 42 0 48 0 014 0 017 0 019 c 0 127 REF 0 005 REF D 5 18 5 28 5 38 0 204 0 208 0 212 E 7 70 7 90 8 10 0 303 0 311 0 319 E1 5 18 5 28 5 38 0 204 0 208 0 212 e 1 27 0 050 L 0 50 0 65 0 80 0 020 0 026 0 031 y 0 10 0 004 θ 0 8 0 8 ...

Page 71: ...e DA SYMBO L MILLIMETERS INCHES Min Nom Max Min Nom Max A 5 33 0 210 A1 0 38 0 015 A2 3 18 3 30 3 43 0 125 0 130 0 135 D 9 02 9 27 10 16 0 355 0 365 0 400 E 7 62 BSC 0 300 BSC E1 6 22 6 35 6 48 0 245 0 250 0 255 L 2 92 3 30 3 81 0 115 0 130 0 150 eB 8 51 9 02 9 53 0 335 0 355 0 375 θ 0 7 15 0 7 15 ...

Page 72: ...030 0 031 A1 0 00 0 02 0 05 0 000 0 001 0 002 b 0 35 0 40 0 48 0 014 0 016 0 019 C 0 20 REF 0 008 REF D 5 90 6 00 6 10 0 232 0 236 0 240 D2 3 35 3 40 3 45 0 132 0 134 0 136 E 4 90 5 00 5 10 0 193 0 197 0 201 E2 4 25 4 30 4 35 0 167 0 169 0 171 e 2 1 27 BSC 0 050 BSC L 0 55 0 60 0 65 0 022 0 024 0 026 y 0 00 0 075 0 000 0 003 ...

Page 73: ...6 Notes 1 Advanced Packaging Information please contact Winbond for the latest minimum and maximum specifications 2 BSC Basic lead spacing between centers 3 Dimensions D and E do not include mold flash protrusions and should be measured from the bottom of the package 4 The metal pad area on the bottom center of the package is connected to the device ground GND pin Avoid placement of exposed PCB vi...

Page 74: ...A1 0 00 0 02 0 05 0 000 0 001 0 002 b 0 20 0 25 0 30 0 008 0 010 0 012 C 0 15 REF 0 006 D 1 90 2 00 2 10 0 075 0 079 0 083 D2 1 55 1 60 1 65 0 061 0 063 0 065 E 2 90 3 00 3 10 0 114 0 118 0 122 E2 0 15 0 20 0 25 0 006 0 008 0 010 e 0 50 0 020 L 0 40 0 45 0 50 0 016 0 018 0 020 L1 0 10 0 004 L3 0 30 0 35 0 40 0 012 0 014 0 016 y 0 000 0 075 0 000 0 003 PIN 1 INDENT D E A A1 y D2 L3 E 2 L1 e b L C ...

Page 75: ...Min Nom Max A 1 20 0 047 A1 0 25 0 30 0 35 0 010 0 012 0 014 A2 0 85 0 033 b 0 35 0 40 0 45 0 014 0 016 0 018 D 7 90 8 00 8 10 0 311 0 315 0 319 D1 4 00 BSC 0 157 BSC E 5 90 6 00 6 10 0 232 0 236 0 240 E1 4 00 BSC 0 157 BSC SE 1 00 TYP 0 039 TYP SD 1 00 TYP 0 039 TYP e 1 00 BSC 0 039 BSC Note Ball land 0 45mm Ball Opening 0 35mm PCB ball land suggested 0 35mm ...

Page 76: ... SYMBOL MILLIMETERS INCHES Min Nom Max Min Nom Max A 1 20 0 047 A1 0 25 0 30 0 35 0 010 0 012 0 014 b 0 35 0 40 0 45 0 014 0 016 0 018 D 7 95 8 00 8 05 0 313 0 315 0 317 D1 5 00 BSC 0 197 BSC E 5 95 6 00 6 05 0 234 0 236 0 238 E1 3 00 BSC 0 118 BSC e 1 00 BSC 0 039 BSC ...

Page 77: ...ature enabled devices P please specify when placing orders W 1 25Q 80B V xx 2 W Winbond 25Q SpiFlash Serial Flash Memory with 4KB sectors Dual Quad I O 80B 8M bit V 2 7V to 3 6V G Green Package Lead free RoHS Compliant Halogen free TBBA Antimony Oxide free Sb2O3 P Green Package with Status Register Power Down OTP enabled 3 4 SN SOIC 8 150 mil SV VSOP 8 150 mil ZP WSON 8 6x5 mm UX USON 8 2x3 mm SS ...

Page 78: ... SS SOIC 8 208mil 8M bit W25Q80BVSSIG W25Q80BVSSIP 25Q80BVSIG 25Q80BVSIP ST 3 VSOP 8 208mil 8M bit W25Q80BVSTIG W25Q80BVSTIP 25Q80BVTIG 25Q80BVTIP ZP 1 WSON 8 6x5mm 8M bit W25Q80BVZPIG W25Q80BVZPIP 25Q80BVIG 25Q80BVIP UX 2 3 USON 8 2x3mm 8M bit W25Q80BVUXIG W25Q80BVUXIP 8Dxxx 0Gxxxx 8Dxxx 0Pxxxx DA PDIP 8 300mil 8M bit W25Q80BVDAIG W25Q80BVDAIP 25Q80BVAIG 25Q80BVAIP TB 3 TFBGA 24 8x6mm 5x5 1 ball ...

Page 79: ...t W25Q80BVZPBG W25Q80BVZPBP 25Q80BVBG 25Q80BVBP UX 2 4 USON 8 2x3mm 8M bit W25Q80BVUXBG W25Q80BVUXBP 8Dxxx 0Gxxxx 8Dxxx 0Pxxxx Part Numbers for Automotive Grade 2 Temperature 3 PACKAGE TYPE DENSITY PRODUCT NUMBER TOP SIDE MARKING SN SOIC 8 150mil 8M bit W25Q80BVSNAG W25Q80BVSNAP 25Q80BVNAG 25Q80BVNAP SS SOIC 8 208mil 8M bit W25Q80BVSSAG W25Q80BVSSAP 25Q80BVSAG 25Q80BVSAP ZP 1 2 WSON 8 6x5mm 8M bit...

Page 80: ... Corporation All other marks are the property of their respective owner Important Notice Winbond products are not designed intended authorized or warranted for use as components in systems or equipment intended for surgical implantation atomic energy control instruments airplane or spaceship instruments transportation instruments traffic signal instruments combustion control instruments or for oth...

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