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WIN Enterprises PL-80930, User Manual

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WIN Enterprises PL-80930 User Manual Download Page 39

Flow Control

Flow control can prevent data loss from buffer overflow. When sending data, if the

receiving buffers are full, a 'stop' signal can be sent to stop the data flow. Once the

buffers are empty, a 'start' signal can be sent to re-start the flow. Hardware flow

control uses two wires to send start/stop signals.

VT - UTF8 Combo Key Support

Enable VT-UTF8 Combination Key Support for ANSI/VT100 terminals.

Recorder Mode

With this mode enabled only text will be sent. This is to capture Terminal data.

Resolution 100x31

Enables or disables extended terminal resolution.

Legacy OS Redirection Resolution

On Legacy OS, the Number of Rows and Columns supported redirection.

Putty KeyPad

Select FunctionKey and KeyPad on Putty.

Redirection After BIOS POST

The Settings specify if BootLoader is selected than Legacy console redirection is

disabled before booting to Legacy OS. Default value is Always Enable which means

Legacy console Redirection is enabled for Legacy OS.

Summary of Contents for PL-80930

Page 1: ...612 PCH Network System support DDR4 up to 256GB 4 PCIe x8 slot for expansion NIC module 2 x 2 5 or 1 x 2 5 1 x 3 5 SATA HDD 2 USB 2 GbE 1 Console CF SATA DOM 1 PCIe x8 slot Redundant PSU PL 80930 Cust...

Page 2: ...Revision History Date Version Modification Editor 2015 12 24 1 0 First Release Jason Fan...

Page 3: ...of International Business Machine Corporation Award is a trademark of Award Software International Inc Intel is a trademark of Intel RTL is a trademark of Realtek VIA is a trademark of VIA Technologie...

Page 4: ...ion module with four GbE copper supports two pairs Gen 3 bypass 3 3 IP 384A Expansion module with eight GbE fiber 3 4 IP 385A Expansion module with eight GbE copper supports two pairs Gen 3 bypass 3 5...

Page 5: ...Chapter 5 Utility Driver Installation 5 1 Operating System Support 5 2 System Driver Installation 5 3 LAN Driver Installation Appendix Appendix A Linux DOS Sample code Appendix B Cable Development Kit...

Page 6: ...t up to 8 NIC modules and support multiple Ethernet module bays for flexible port configuration such as 10 Gigabit SFP Gigabit copper with BYPASS function or not and Gigabit fiber ports Maximum capabl...

Page 7: ...ion module with 8 RJ45 GbE ports with two pairs Gen 3 bypass Intel I350 AM4 IP 386A Expansion module with 4 SFP 10 GbE ports Intel XL710 BM1 w o re driver IP 387A Expansion module with 2 QSFP 40 GbE p...

Page 8: ...ttons LED 4x GPO LEDs via R 380A GP57 Yellow GP54 Yellow GP55 R ed GP56 Green Dimensions W x D x H 440mm W x 570mm D x 44mm H 17 2 W x 22 44 D x 1 73 H Operating Temperature Operating 0 40 C 32 104 F...

Page 9: ...s Intel X540 BT2 IP 408B Expansion module with 2 RJ45 10G ports Intel X540 BT2 DK002 Cable development kit CB CO5204 00 Cross over 2M CB DB9200 01 Null modem cable 2M CB EC5200 00 Ethernet cat 5 cable...

Page 10: ...near future After you unpack the goods inspect and make sure the packaging is intact Do not plug the power adapter to the appliance if you find it appears damaged Note Keep the PL 80930 in the origina...

Page 11: ...eappliance Do not remove the anti static packing until you are ready to install the PL 80930 appliance Ground yourself before removing any system component from its protective anti static packaging To...

Page 12: ...1 6 System Layout Front panel features Rear panel features...

Page 13: ...1 7 Dimensions...

Page 14: ...1 Connector Pin Define and Jumper Setting Connector List Connector Define CN1 VR12_I2C PIN HEADER CN2 USB PIN HEADER CN3 VGA BOX HEADER CN4 ATX_SWITCH CN5 CPLD JTAG CN6 DEBUG GPIO CN7 ATX I2C Connecto...

Page 15: ...A3 2 CN22 SATA3 1 CN23 SATA3 3 CN24 USB3 0 PIN HEADER CN25 SATA3 4 CN26 PCIE X8 SLOT CN27 PCIE X8 SLOT CN28 PCIE X8 SLOT CN29 PCIE X8 SLOT CN30 PCIE X8 SLOT CN31 I O Connector CN33 SATA DOM PWR CN34 V...

Page 16: ...SYSTEM FAN 2 1U FAN9_4 SYSTEM FAN 2 1U FAN10_5 SYSTEM FAN 2 1U CN1 VR12_I2C PIN Description 1 GND 2 DATA 3 CLK CN2 CN48 USB2 0 PIN HEADER PIN Description PIN Description 1 5V 2 5V 3 USB_CON_PN2 4 USB_...

Page 17: ...on PIN Description 1 CPLD_TCK 2 GND 3 CPLD_TDO 4 3 3V_AUX 5 CPLD_TMS 6 NC 7 NC 8 NC 9 CPLD_TDI 10 GND CN6 DEBUG GPIO PIN Description 1 GPIO57 2 GND CN10 ATX I2C Connector PIN Description 1 CLK 2 DAT 3...

Page 18: ...DER PIN Description PIN Description 1 3 3V 2 LPC_AD0 3 LPC_AD1 4 LPC_AD2 5 LPC_AD3 6 FRAME_N 7 RST_LPC 8 5V 9 CLK_33MHZ 10 PME_N 11 GND 12 NC 13 SERIRQ 14 LDRQ1 CN17 KEY PAD PIN HEADER PIN Description...

Page 19: ...DAT 4 L_MDAT 5 NC 6 NC 7 GND 8 GND 9 5V 10 5V CN23 PCIE 12V_ATX4PIN RESERVED PIN Description PIN Description 1 GND 3 12V 2 GND 4 12V CN24 GPO PIN HEADER PIN Description PIN Description 1 SIO_GP70 2 3...

Page 20: ...PD0 9 PD3 10 PD2 11 PD5 12 PD4 13 PD7 14 PD6 15 BK_CTRLN 16 BK_CTRLP CN28 ATX 24PIN PIN Description PIN Description 1 3 3V 13 3 3V 2 3 3V 14 12V 3 GND 15 GND 4 5V 16 PS_ON 5 GND 17 GND 6 5V 18 GND 7...

Page 21: ...3_TX1_P 5 USB3_TX0_N 15 USB3_TX1_N 6 USB3_TX0_P 16 GND 7 GND 17 USB3_RX1_P 8 USB2_PN0 18 USB3_RX1_N 9 USB2_PP0 19 5V 10 NC 20 NC CN35 CN36 CN37 CN38 CN40 PCIE X8 SLOT CN45 I O Connector PIN Descriptio...

Page 22: ...LAN2_CON_1N 27 SIO_GP55 28 LAN2_CON_2P 29 SIO_GP56 30 LAN2_CON_2N 31 SIO_GP57 32 LAN2_CON_3P 33 HDD_LED_N 34 LAN2_CON_3N 35 RIA_N2 36 3 3V_AUX 37 DTR_N2 38 P80_CTRL 39 GND 40 RESET_BTN _NMI CN47 SATA...

Page 23: ...JP2 ATX AT SELECT 1 2 ATX DEFAULT 2 3 AT JP3 H W OR S W RESET 1 2 H W RESET DEFAULT 2 2 S W RESET JP4 CLEAR CMOS 1 2 Normal DEFAULT 2 3 Clear CMOS JP6 BYPASS LED OR GPIO LED 1 2 GPIO54 DEFAULT 2 3 ALL...

Page 24: ...ter 3 Optional LAN Module Add on Card Settings 3 1 IP 384A Expansion module with 8 SFP GbE ports Intel 82580EB 3 2 IP 385A Expansion module with 8 RJ45 GbE ports with two pairs Gen 3 bypass Intel 8258...

Page 25: ...3 3 IP 386A Expansion module with 4 SFP 10 GbE ports Intel XL710 B M1 w o re driver 3 4 IP 387A Expansion module with 2 Q SFP 40 GbE ports Intel XL710 B M2 w o re driver...

Page 26: ...3 5 IP 405A Expansion module with 4 SFP GbE ports Intel i350 AM4 3 6 IP 406A Expansion module with 4 RJ45 GbE ports with two pairs Gen 3 bypass Intel i350 A M4...

Page 27: ...th 4 RJ45 10G ports Intel X540 BT 2 3 8 IP 408B Expansion module with 2 RJ45 10G ports Intel X540 BT2 3 9 IP 380A Front I O module IP 380A is a front I O module with GPO LEDs two USB 2 0 port one RJ45...

Page 28: ...or Date and time Memory capacity of the appliance Type of display adapter installed Number and type of disk drives The CMOS memory is maintained by battery installed on the PL 80930 board By using the...

Page 29: ...t for a long time Find the original setup missing Replace the battery Change to a different type of CPU Run the AMI Flash program to update the system BIOS Run the BIOS setup program after you turn on...

Page 30: ...anges and reboot the system Press F3 Optimized Defaults to load the Optimal default configuration values of the menu Pressing ESC anywhere in the program returns you to the main menu 4 3 Menu Options...

Page 31: ...ollows 1 Choose Advanced from the main menu The following screen appears 2 Use the arrow keys to move between fields Modify the selected field using the PgUP PgDN keys Some fields let you enter numeri...

Page 32: ...4 4 1 Platform Function SOL Switch Switch Console for COM2 or SOL Watch dog Mode Watch dog Mode Sec Min Watch dog Timer Watch dog Mode Sec Min...

Page 33: ...4 4 2 LAN Bypass Function...

Page 34: ...4 4 3 NCT6791D Super IO Configuration...

Page 35: ...Serial Port 1 Configuration Set Parameters of Serial Port 1 Serial Port 2 Configuration Set Parameters of Serial Port 2 Serial Port Enables or Disables Serial Port Change Setting Device Settings...

Page 36: ...4 4 4 System Hardware Monitor...

Page 37: ...rial Port Console Redirection Legacy Serial Redirection Port Select a COM port to display redirection of Legacy OS and Legacy OPROM Messages COM0 COM1 Console Redirection Console Redirection Enable or...

Page 38: ...Data Bits Data Bits Parity A parity bit can be sent with the data bits to detect some transmission errors Even parity bit is 0 if the num of 1 s in the data bits is even Odd parity bit is 0 if num of...

Page 39: ...r ANSI VT100 terminals Recorder Mode With this mode enabled only text will be sent This is to capture Terminal data Resolution 100x31 Enables or disables extended terminal resolution Legacy OS Redirec...

Page 40: ...bles or Disables 64bit capable Devices to be Decoded in Above 4G Address Space Only if System Supports 64 bit PCI Decoding SR IOV Support If system has SR IOV capable PCIe Devices this option Enables...

Page 41: ...um Payload of PCI Express Device or allow System BIOS to select the value Extended Synch If ENABLED allows generation of Extended Synchronization patterns Lin k Training Retry Defines number of Retry...

Page 42: ...mpletion Timeout In device Functions that support Completion Timeout programmability allows system software to modify the Completion Timeout value Default 50us to 50ms If Shorter is selected software...

Page 43: ...refix Blocking If supported by hardware and set to Enabled this function will block forwarding of TLPs containing End End TLP Prefixes Clock Power Management If supported by hardware and set to Enable...

Page 44: ...tive UPON REQUEST GA20 can be disabled using BIOS services ALWAYS do not allow disabling GA20 this option is useful when any RT code is executed above 1MB Option ROM Messages Set display mode for Opti...

Page 45: ...4 4 8 USB Configuration...

Page 46: ...for OSes without EHCI hand off support The EHCI ownership change should be claimed by EHCI driver USB Mass Storage Driver Support Enable Disable USB Mass Storage Driver Support USB transfer time out...

Page 47: ...nd provides option to change the Common RefCode Settings QPI Configuration Displays and provides option to change the QPI Settings Memory Configuration Displays and provides option to change the Memor...

Page 48: ...4 5 1 Processor Configuration Hyper threading Enabled for Windows XP and Linux OS optimized for Hyper Threading Technology...

Page 49: ...3 VMX Enables the Vanderpool Technology takes effect after reboot Hardware Prefetcher Enable the Mid Level Cache L2 streamer prefetcher Adjacent Cache Prefetc h MLC Spatial Prefetcher DCU Streamer Pr...

Page 50: ...4 5 1 1 CPU Core Configuration...

Page 51: ...d Cores available In STR_CORE_ENABLE_HELP d will be replaced with number of cores IOT Cfg Cbo Bitmap Each bit enables IOT OCLA for a CBo 4 5 2 Advanced Power Management Configuration Power Technology...

Page 52: ...PU frequency according load When disabled CPU frequency is set at max non turbo Turbo Mode Turbo mode allows a CPU logical processor to execute a higher frequency when enough power is available not ex...

Page 53: ...ot P a ckage C State limit Package C State limit CPU C3 report Enable Disable CPU C3 ACPI C2 report to OS Recommended to be disabled CPU C6 report Enable Disable CPU C6 ACPI C2 report to OS Recommende...

Page 54: ...4 5 2 3 CPU Advanced PM Tuning 4 5 2 3 1 Energy Perf BIAS Energy Performance BI Set Energy Performance BIAS which overrides OS setting...

Page 55: ...of the average for C0 and P0 time P0 TotalTimeThreshold Low The HW switching mechanism DISABLES the performance setting 0 when the total P0 time is less than this threshhold P0 TotalTimeThreshold High...

Page 56: ...ble or Enable Meseg Mode Numa Enable or Disable Non uniform Memory Access NUMA 4 5 4 QPI Configuration QPI General Configuration Displays and provides option to change the QPI General Settings CPU QPI...

Page 57: ...ology if system options are in conflict Link Frequency Select Allows for selecting the QPI Link Frequency Link L0p Enable Link L0p Enable Disable Enable Auto default Link L1 Enable Link L1 Enable Disa...

Page 58: ...Enable disable Home Dir Snoop with IVT Style OSB QPI Debug Print Level QPI Debug Print Level Enable Disable 4 5 4 1 1 QPI Status...

Page 59: ...4 5 4 2 CPU QPI Configuration CPU QPI QPI Per Socket Configuration...

Page 60: ...cation Bus resources allocation ratio range 0 to 8 IO Resources Allocation IO resources allocation ratio range 0 to 8 MMIOL Resources Allocation MMIOL resources allocation ratio range 0 to 8 IIO Disab...

Page 61: ...4 5 5 Memory Configuration...

Page 62: ...ximum Memory Frequency Selections in Mhz Do not select Reserved MRC Promote Warnings Determines if MRC warnings are promoted to system level Promote Warnings If enabled RC warnings are promoted to err...

Page 63: ...test loops during normal boot set to 0 to run memtest infinitely Dram Maintenance Test Dram Maintenance Test during normal boot Dram Maintenance Test Direction Dram Maintenance Test Direction UP or D...

Page 64: ...d Memtest on Fast Boot Enable disable memory test during fast boot RMT on Cold Fast Boot Enable Disable Rank Margin Tool on Cold Fast Boot BDAT Enable Disables BDAT Data Scrambling Enables data scramb...

Page 65: ...Enable Disable issuing read commands opportunistically during WMM Normal Operation Duration Set normal operation duration interval 0 65535 Number of Sparing Transactions Set number of sparing transac...

Page 66: ...4 5 6 IIO Configuration...

Page 67: ...on reads and writes for Vc0 traffic Gen3 Phase3 Loop Count Gen3 Phase3 Loop Count 1 4 16 256 Skip Halt On DMI Degradation Enable this option to avoid the system to be halted on DMI width link degradat...

Page 68: ...4 5 6 1 IIO Configuration 4 5 6 1 1 Socket 0 PcieD00F0 Port 0 DMI...

Page 69: ...option enables disables the ASPM L1 for the downstream devices PCI E Port L0s Exit Latency The length of time this port requires to complete transition from L0s to L0 PCI E Port L1 Exit Latency The le...

Page 70: ...4 5 6 1 2 Socket 0 PcieD01F0 Port 1A...

Page 71: ...on enables disables the ASPM L1 for the downstream devices PCI E Port L0s Exit Latency The length of time this port requires to complete transition from L0s to L0 PCI E Port L1 Exit Latency The length...

Page 72: ...tream Tx Preset Gen3 DN Rx Preset Hint PCIe Gen3 Downstream Rx Preset Hint Gen3 UP Tx Preset PCIe Gen3 Upstream Tx Preset Hide Port User can force to hide this root port from OS 4 5 6 1 3 Socket 0 Pci...

Page 73: ...ational speed by restricting the values advertised by the Upstream component in its training sequences When Auto is selected HW initialized data will be used Override Max Link Wid Override the max lin...

Page 74: ...error propogation to the IIO core error logic for this port L0s Support When disabled IIO never puts its transmitter in L0s state PM ACPI Mode When Disabled MSI is generated on PM event When Enabled _...

Page 75: ...4 5 6 1 4 Socket 0 PcieD02F2 Port 2C...

Page 76: ...ion enables disables the ASPM L1 for the downstream devices PCI E Port L0s Exit Latency The length of time this port requires to complete transition from L0s to L0 PCI E Port L1 Exit Latency The lengt...

Page 77: ...et PCIe Gen3 Downstream Tx Preset Gen3 DN Rx Preset Hint PCIe Gen3 Downstream Rx Preset Hint Gen3 UP Tx Preset PCIe Gen3 Upstream Tx Preset Hide Port User can force to hide this root port from OS 4 5...

Page 78: ...tional speed by restricting the values advertised by the Upstream component in its training sequences When Auto is selected HW initialized data will be used Override Max Link Wid Override the max link...

Page 79: ...lization Mode Gen3 Spec Mode PCIe Gen3 Spec Mode Gen3 Phase2 Mode Gen3 Phase2 Mode Gen3 DN Tx Preset PCIe Gen3 Downstream Tx Preset Gen3 DN Rx Preset Hint PCIe Gen3 Downstream Rx Preset Hint Gen3 UP T...

Page 80: ...2 or 39 disables BAR Secondary BAR 4 Size Used to set the prefetchable BAR 4 size on Secondary side of NTB Value than 12 or 29 39 for BIOS supporting 4G PCI disables BAR Secondary BAR 5 Size Used to s...

Page 81: ...ational speed by restricting the values advertised by the Upstream component in its training sequences When Auto is selected HW initialized data will be used Override Max Link Wid Override the max lin...

Page 82: ...to the IIO core error logic for this port L0s Support When disabled IIO never puts its transmitter in L0s state PM ACPI Mode When Disabled MSI is generated on PM event When Enabled _HPGPE message is...

Page 83: ...4 5 6 2 IIO General Configuration IIO IOAPIC Enable Disable the IIO IOAPIC...

Page 84: ...gnment to VMM through DMAR ACPI Tables ACS Control Enable Programs ACS only to Chipset Pcie Root Ports Bridges Disable Programs ACS to all Pcie bridges Interrupt Remapping Enable Disable VT_D Interrup...

Page 85: ...4 5 7 PCH Configuration 4 5 7 1 PCH Devices...

Page 86: ...r a G3 4 5 7 2 PCI Express Configuration PCI E ASPM Support This option enables disables the ASPM support for all downstream devices PCIE Clock Gating PCIE Clock Gating Enable Disable for all PCH PCIE...

Page 87: ...1 Substates settings PME SCI PCI Express PME SCI Enable Disable Hot Plug Designates this port as Hot Pluggable PCIe Speed Configure PCIe Speed PME Interrupt PCI Express PME Interrupt Enable Disable Ex...

Page 88: ...trol the PCI Express Root Port PCH PCIE ASPM PCI Express Root port ASPM Setting L1 Substates PCI Express L1 Substates settings PME SCI PCI Express PME SCI Enable Disable Hot Plug Designates this port...

Page 89: ...ry Reserved Memory and Prefetchable Memory 1 20MB Range for this Root Bridge Reserved I O Reserved I O 4K 8K 12K 16K 20K Range for this Root Bridge 4 5 7 2 3 PCI Express Root Port 3 PCI Express Root P...

Page 90: ...ed 0 7 for bridges behind this Root Bridge Reserved Memory Reserved Memory and Prefetchable Memory 1 20MB Range for this Root Bridge Prefetchable Memory Reserved Memory and Prefetchable Memory 1 20MB...

Page 91: ...PME Interrupt PCI Express PME Interrupt Enable Disable MSI PCIE MSI Enable Disable Extra Bus Reserved Extra Bus Reserved 0 7 for bridges behind this Root Bridge Reserved Memory Reserved Memory and Pr...

Page 92: ...ting L1 Substates PCI Express L1 Substates settings PME SCI PCI Express PME SCI Enable Disable Hot Plug Designates this port as Hot Pluggable PCIe Speed Configure PCIe Speed PME Interrupt PCI Express...

Page 93: ...Root Bridge Reserved I O Reserved I O 4K 8K 12K 16K 20K Range for this Root Bridge 4 5 7 2 6 PCI Express Root Port 6 PCI Express Root Port Control the PCI Express Root Port PCH PCIE ASPM PCI Express...

Page 94: ...ory Reserved Memory and Prefetchable Memory 1 20MB Range for this Root Bridge Prefetchable Memory Reserved Memory and Prefetchable Memory 1 20MB Range for this Root Bridge Reserved I O Reserved I O 4K...

Page 95: ...Interrupt Enable Disable MSI PCIE MSI Enable Disable Extra Bus Reserved Extra Bus Reserved 0 7 for bridges behind this Root Bridge Reserved Memory Reserved Memory and Prefetchable Memory 1 20MB Range...

Page 96: ...Substates PCI Express L1 Substates settings PME SCI PCI Express PME SCI Enable Disable Hot Plug Designates this port as Hot Pluggable PCIe Speed Configure PCIe Speed PME Interrupt PCI Express PME Inte...

Page 97: ...mory 1 20MB Range for this Root Bridge Prefetchable Memory Reserved Memory and Prefetchable Memory 1 20MB Range for this Root Bridge Reserved I O Reserved I O 4K 8K 12K 16K 20K Range for this Root Bri...

Page 98: ...es Link Power Management Port 0 1 2 Enable or Disable SATA Port Spin Up Device If enabled for any of ports Staggered Spin Up will be performed and only the drives which have this option enabled will s...

Page 99: ...4 5 7 3 1 SATA Mode Options SATA Led locate If enabled LED SGPIO hardware is attached...

Page 100: ...4 5 7 4 PCH SATA Configuration...

Page 101: ...Link Power Management SATA Port 0 1 2 3 4 5 SATA Port 0 1 2 3 4 5 Software Preserve Software Preserve Port 0 1 2 3 4 5 Enable or Disable SATA Port Configure as eSATA Configures port as External SATA e...

Page 102: ...entify the SATA port is connected to Solid State Drive or Hard Disk Drive 4 5 7 4 1 SATA Mode Options SATA HDD Unlock Enable HDD password unlock is enabled in the OS SATA Led locate If enabled LED SGP...

Page 103: ...TCG USB Ports Per Port Control each of the USB ports 0 13 disabling XHCI Idle L1 Enabled XHCI Idle L1 Disabled to workaround USB3 hot plug will fail after 1 hot plug removal Please put the system to G...

Page 104: ...Enable Disable the PCH GPIO Lockdown feature RTC Lock Enable will lock bytes 38h 3Fh in the lower upper 128 byte bank of RTC RAM BIOS Lock Enable Disable the PCH BIOS Lock Enable feature Host Flash L...

Page 105: ...y Bus Number Specify the PCI minimum secondary bus number in system PCIe Extended Tag Enable Enable or Disable Extended Tag Enable Field Support PCIe AtomicOp Request Enable or disable AtomicOp Reques...

Page 106: ...4 6 Server Mgmt...

Page 107: ...BMC Wait For BMC response for specified time out In PILOTII BMC starts at the same time when BIOS starts during AC power ON It takes around 30 seconds to initialize Host to BMC interfaces BMC Warm Re...

Page 108: ...press the F1 key for information on the various options 3 After you have finished with the Security setup press the or key to switch to other setup menu or press F4 key to save setting Administrator...

Page 109: ...is set to Disabled the BIOS displays normal POST messages If Enabled an OEM Logo is shown instead of POST messages CDROM DVD Drive BBS Priorities Specifies the Boot Device Priority sequence from avai...

Page 110: ...n menu the following screen appears 2 Move between items and select values by using the arrow keys Modify the selected fields using the PgUP PgDN keys For information on the various options please pre...

Page 111: ...ease install the GbE modules properly before you install the OS driver or other software 5 1 Operation System Supporting PL 80930 can support Windows and Linux operating systems as follows Before inst...

Page 112: ...ase click the Autorun file and install the driver following the procedures 1 Insert the setup CD of PL 80930into your CD ROM drive 2 Choose the Drivers file to click the Autorun icon 3 Follow the proc...

Page 113: ...able 2M RoHS CB EC5200 00 1 Cross Over 2M Color RoHS CB CO5202 4 00 1 RJ45 to DB9 2M Cable RoHS CB RJDB91 00 1 2m null modem cable RoHS CB DB9200 01 1 VGA CABLE 2mm 15CM RoHS CB IVGA01 00 1 KB MS CABL...

Page 114: ...parts and recycling This symbol of the crossed out wheeled bin indicates that the product electrical and electronic equipment should not be placed in municipal waste Check local regulations for the d...

Page 115: ...ear adjustable brackets Loosen the nuts on the both brackets and decide the proper setback distance to the opening then tighten the nuts on the front brackets Step 3 Extend the rear brackets to where...

Page 116: ...orward to secure the bracket It is important to check if the safety lock is in unlocked position before mounting the brackets Step 5 Attach the inner slide member to your chassis Attach the inner slid...

Page 117: ...the chassis into the cabinet Pick up your chassis Insert your chassis with inner slide member into the intermediate member The chassis will be locked when it reaches the fully open position then pull...

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