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WDC 65 Series, Datasheet

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November 09, 2018

 

 

 

 

 

33 

 
 

Table 5-5 continued 

M

ne

m

o

ni

c

 

Operation 

OpCodes 

Status Register 

Addressing Mode 

 

7 

6 

5 

4 

3 

2 

1 

0 

a

 

A

 

a

,x

 

a

,y

 

al

 

a

l,x

 

(a

) 

(a

,x)

 

d

 

d

,s

 

d

,x

 

d

,y

 

(d

) 

[d

] 

(d

,s)

,

y

 

(d

,x)

 

(d

),y

 

[d

],

y

 

i 

r 

rl

 

s

 

xyc

 

#

 

N 

V 

M  X 

D 

I 

Z 

C 

1 

2 

3 

4 

5 

6 

7 

8 

9 

10  11  12  13  14  15  16  17  18  19  20  21  22  23  24 

N 

V 

1 

B 

D 

I 

Z 

C 

LDX 

M 

 X 

AE 

 

 

BE 

 

 

 

 

A6 

 

 

B6 

 

 

 

 

 

 

 

 

 

 

 

A2 

N 

. 

. 

. 

. 

. 

Z 

. 

LDY 

M 

 Y 

AC 

 

BC 

 

 

 

 

 

A4 

 

B4 

 

 

 

 

 

 

 

 

 

 

 

 

A0 

N 

. 

. 

. 

. 

. 

Z 

. 

LSR 

0 

 

15/7 6 … 1 0 

 C 

4E  4A  5E   

 

 

 

 

46 

 

56 

 

 

 

 

 

 

 

 

 

 

 

 

 

0 

. 

. 

. 

. 

. 

Z 

C 

MVN* 

M

M NEGATIVE 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

54 

 

. 

. 

. 

. 

. 

. 

. 

. 

MVP* 

M

M POSITIVE 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

44 

 

. 

. 

. 

. 

. 

. 

. 

. 

NOP 

No Operation 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

EA 

 

 

 

 

 

. 

. 

. 

. 

. 

. 

. 

. 

ORA 

A V M 

 A 

0D 

 

1D  19 

0F  1F 

 

 

05 

03 

15 

 

12 

07 

13 

01 

11 

17 

 

 

 

 

 

09 

N 

. 

. 

. 

. 

. 

Z 

. 

PEA* 

Mpc+1, Mpc+2 → Ms-1, Ms 
S-

2  → S

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

F4 

 

 

. 

. 

. 

. 

. 

. 

. 

. 

PEI* 

M(d), M(d+1) → Ms-1, Ms 
S-

2  →  S

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

D4 

 

 

. 

. 

. 

. 

. 

. 

. 

. 

PER* 

Mpc+rl,  Mpc+rl+1  →  Ms-1, 
Ms S-

2  → S

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

62 

 

 

. 

. 

. 

. 

. 

. 

. 

. 

PHA 

A 

 Ms, S-1 

 S 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

48 

 

 

. 

. 

. 

. 

. 

. 

. 

. 

PHB* 

DBR →  Ms, S-1 → S 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

8B 

 

 

. 

. 

. 

. 

. 

. 

. 

. 

PHD* 

D → Ms, Ms-1, S-2 → S 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0B 

 

 

. 

. 

. 

. 

. 

. 

. 

. 

PHK* 

PBR →  Ms, S-1 → S 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4B 

 

 

. 

. 

. 

. 

. 

. 

. 

. 

PHP 

P 

 Ms, S-1 

 S 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

08 

 

 

. 

. 

. 

. 

. 

. 

. 

. 

PHX 

X 

 Ms, S-1 

 S 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DA 

 

 

. 

. 

. 

. 

. 

. 

. 

. 

PHY 

Y 

 Ms, S-1 

 S 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

5A 

 

 

. 

. 

. 

. 

. 

. 

. 

. 

PLA 

S + 1 

 S, Ms 

 A 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

68 

 

 

N 

. 

. 

. 

. 

. 

Z 

. 

PLB

 

S + 1 

 S, Ms 

 DBR 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

AB 

 

 

N 

. 

. 

. 

. 

. 

Z 

. 

PLD

 

S + 2 

  S, Ms 

– 1, Ms 

→ D 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2B 

 

 

N 

. 

. 

. 

. 

. 

Z 

. 

PLP 

S + 1 

 S, Ms 

 P 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

28 

 

 

N 

V 

M  X 

D 

1 

Z 

C 

PLX 

S + 1 

 S, Ms 

 X 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

FA 

 

 

N 

. 

. 

. 

. 

. 

Z 

. 

PLY 

S + 1 

 S, Ms 

 Y 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

7A 

 

 

N 

. 

. 

. 

. 

. 

Z 

 

REP

 

M^P 

 P 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

C2 

N 

V 

M  X 

D 

1 

Z 

C 

ROL 

C 

 15/7 6 5 4 3 2 1 0 

 C 

2E  2A  3E 

 

 

 

 

 

26 

 

36 

 

 

 

 

 

 

 

 

 

 

 

 

 

N 

. 

. 

. 

. 

. 

Z 

C 

ROR 

C 

15/7  6  5  4  3  2  1  0 

 C 

6E  6A  7E 

 

 

 

 

 

66 

 

76 

 

 

 

 

 

 

 

 

 

 

 

 

 

N 

. 

. 

. 

. 

. 

Z 

C 

RTI 

Return from Interrupt 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

40 

 

 

N 

V 

M  X 

D 

1 

Z 

C 

RTL* 

Return from Sub. 
Long 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

6B 

 

 

. 

. 

. 

. 

. 

. 

. 

. 

RTS 

Return from 
Subroutine 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

60 

 

 

. 

. 

. 

. 

. 

. 

. 

. 

SBC 

A 

– M – (C) 

 A 

ED 

 

FD  F9 

 

FF 

 

 

E5  E3  F5 

 

F2  E7  F3  E1  F1  F7 

 

 

 

 

 

E9 

N 

V 

. 

. 

. 

. 

Z 

C 

SEC 

1 

 C 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

38 

 

 

 

 

 

. 

. 

. 

. 

. 

. 

. 

1 

SED 

1 

 D 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

F8 

 

 

 

 

 

. 

. 

. 

. 

1 

. 

. 

. 

SEI 

1 

 1 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

78 

 

 

 

 

 

. 

. 

. 

. 

. 

1 

. 

. 

SEP* 

MVP 

 P 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

E2 

N 

V 

M  X 

D 

1 

Z 

C 

STA 

A 

 M 

8D 

 

9D 

 

8F  9F 

 

 

85 

83 

95 

 

92 

87 

93 

81 

91 

97 

 

 

 

 

 

 

. 

. 

. 

. 

. 

. 

. 

. 

STP 

STOP (1 

 PH12) 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

D8 

 

 

 

 

 

. 

. 

. 

. 

. 

. 

. 

. 

STX 

X 

 M 

8E 

 

 

 

 

 

 

 

86 

 

 

96 

 

 

 

 

 

 

 

 

 

 

 

 

. 

. 

. 

. 

. 

. 

. 

. 

 

Summary of Contents for 65 Series

Page 1: ...ery instance it must be the responsibility of the user to determine the suitability of the products for each application WDC products are not authorized for use as critical components in life support devices or systems Nothing contained herein shall be construed as a recommendation to use any product in violation of existing patents or other rights of third parties The sale of any WDC product is s...

Page 2: ... 2 19 Memory Lock MLB 13 2 20 Memory Index Select Status MX 13 2 21 Non Maskable Interrupt NMIB 14 2 22 Phase 2 In PHI2 14 2 23 Read Write RWB 14 2 24 Ready RDY 14 2 25 Reset RESB 15 2 26 Valid Data Address VDA and Valid Program Address VPA 15 2 27 VDD and VSS 15 2 28 Vector Pull VPB 15 3 ADDRESSING MODES 16 3 1 Reset and Interrupt Vectors 16 3 2 Stack 16 3 3 Direct 16 3 4 Program Address Space 16...

Page 3: ... Field 48 7 Caveats 49 7 1 Stack Addressing 50 7 2 Direct Addressing 50 7 3 Absolute Indexed Addressing 50 7 4 ABORTB Input 50 7 5 VDA and VPA Valid Memory Address Output Signals 50 7 6 DB BA operation when RDY is Pulled Low 51 7 7 MX Output 51 7 8 All Opcodes Function in All Modes of Operation 51 7 9 Indirect Jumps 51 7 10 Switching Modes 51 7 11 How Interrupts Affect the Program Bank and the Dat...

Page 4: ...ion Mode Vector Locations 8 bit Mode 30 Table 5 3 Native Mode Vector Locations 16 bit Mode 30 Table 5 4 Opcode Matrix 31 Table 5 5 Operation Operation Codes and Status Register 32 Table 6 1 Alternate Mnemonics 46 Table 6 2 Address Mode Formats 47 Table 6 3 Byte Selection Operator 48 Table 7 1 Caveats 49 Table of Figures Figure 2 1 W65C816S Internal Architecture Simplified Block Diagram 8 Figure 2 ...

Page 5: ...ly executing instruction without modifying internal register thus allowing virtual memory system design Valid Data Address VDA and Valid Program Address VPA outputs facilitate dual cache memory by indicating whether a data segment or program segment is accessed Modifying a vector is made easy by monitoring the Vector Pull VPB output 1 1 Features of the W65C816S Advanced fully static CMOS design fo...

Page 6: ...quired to complete the instruction Each data transfer between registers depends upon decoding the contents of both the Instruction Register and the Timing Control Unit 2 3 Arithmetic and Logic Unit ALU All Arithmetic and Logic Unit operations take place within the 16 bit ALU In addition to data operations the ALU also calculates the effective address for relative and indexed addressing modes The r...

Page 7: ...rocessor operations The Emulation E select and the Break B flags are accessible only through the Processor Status Register The Emulation mode select flag is selected by the Exchange Carry and Emulation Bits XCE instruction Table 8 1 W65C816S Compatibility Information illustrates the features of the Native E 0 and Emulation E 1 modes The M and X flags are always equal to one in Emulation mode When ...

Page 8: ...8 BITS INTERNAL DATA BUS 16 BITS DATA LATCH PREDECODER INTERNAL SPECIAL BUS 16 BITS DATA BANK DBR 8 BITS PROG BANK PBR 8 BITS DIRECT D 16 BITS PROG COUNTER PC 16 BITS ACCUMULATOR C 16 BITS A 8 BITS B 8 BITS TRANSFER SWITCHES ALU 16 BITS STACK POINTER S 16 BITS INDEX Y 16 BITS INDEX X 16 BITS ADDRESS BUFFER LOW ADRESS BUFFER HIGH DATA BUS BANK ADDRESS BUFFER INTERNAL ADDRESS BUS 16 BITS A0 A7 A8 A1...

Page 9: ...Program PCH Direct Register DH Direct Register DL Data Bank Register DBR Data Bank Register DBR 00 Program Bank Register PBR 00 Shaded Blocks 6502 registers N V M X D I Z C 1 B E BRK Bit 1 BRK 0 IRQ Carry 1 true Zero 1 result zero IRQ disable 1 disable Decimal mode 1 true Index Register Select 1 8 bit 0 16 bit Memory Select 1 8 bit 0 16 bit Overflow 1 true Negative 1 negative Emulation 1 W65C02 Em...

Page 10: ...11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 W65C816S 2 12 Pin Function Description Figure 2 2 W65C816S 40 Pin DIP Pinout Figure 2 3 W65C816S 44 Pin PLCC Pinout W65C816S 6 5 4 3 2 1 44 43 42 41 40 18 19 20 21 22 23 24 25 26 27 28 NMIB VPA VDD A0 A1 NC A2 A3 A4 A5 A6 MLB IRQB ABORTB RDY VPB VSS RESB VDA MX PHI2 BE E RWB VDD D0 D1 D2 D3 D4 D5 D6 D7 7 8 9 ...

Page 11: ...16 17 18 19 20 21 22 NMIB VPA VDD A0 A1 NC A2 A3 A4 A5 A6 MLB IRQB ABORTB RDY VPB VSS RESB VDA MX PHI2 BE E RWB VDD D0 D1 D2 D3 D4 D5 D6 D7 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 A7 A8 A9 A10 A11 VSS VSS A12 A13 A14 A15 Figure 2 4 W65C816S 44 PIN QFP Pinout ...

Page 12: ... aborted opcode is stored as the return address in stack memory The Abort vector address is 00FFF8 9 Emulation mode or 00FFE8 9 Native mode Note that ABORTB is a pulse sensitive signal i e an abort will occur whenever there is a negative pulse or level on the ABORTB pin during a PHI2 clock 2 14 Address Bus A0 A15 The sixteen Address Bus output lines along with the bank address multiplexed on the f...

Page 13: ...vel sensitive input an interrupt will occur if the interrupt source was not cleared since the last interrupt Also no interrupt will occur if the interrupt source is cleared prior to interrupt recognition The IRQB signal going low causes 4 bytes of information to be pushed onto the stack before jumping to the interrupt handler The first byte is PBR followed by PCH PCL and P Processor Status Registe...

Page 14: ... control whether the microprocessor is Reading or Writing to memory When the RWB is in the high state the microprocessor is reading data from memory or I O When RBW is low the Data Bus contains valid data from the microprocessor which is to written to the addressed memory location The RWB signal is set to the high impedance state when Bus Enable is low 2 24 Ready RDY The Ready is a bi directional ...

Page 15: ...s The Reset vector address is 00FFFC D see Table 6 1 for Vectors PC is loaded with the contents of 00FFFC D 2 26 Valid Data Address VDA and Valid Program Address VPA The Valid Data Address and Valid Program Address output signals indicate valid memory addresses when high and are used for memory or I O address qualification VDA VPA 0 0 0 1 1 0 1 1 Internal Operation Address and Data Bus available T...

Page 16: ...Absolute Indirect and Absolute Indexed Indirect addressing modes or by incrementing the Program Counter from FFFF The only instructions that affect the Program Bank register are RTI RTL JML JSL and JMP Absolute Long Program code may exceed 64K bytes although code segments may not span bank boundaries 3 5 Data Address Space The Data Address space is contiguous throughout the 16 MByte address space ...

Page 17: ...ion Opcode addrl addrh addrh addrl X Reg PBR address then PC address 3 5 3 Absolute Indexed with X a x With Absolute Indexed with X a x addressing the second and third bytes of the instruction are added to the X Index Register to form the low order 16 bits of the effective address The Data Bank Register contains the high order 8 bits of the effective address Instruction Opcode addrl addrh DBR addr...

Page 18: ...ng Indexed With X al x With Absolute Long Indexed with X al x addressing the second third and fourth bytes of the instruction form a 24 bit base address The effective address is the sum of this 24 bit address and the X Index Register Instruction Opcode addrl addrh baddr baddr addrh addrl X Reg Operand Address effective address 3 5 7 Absolute Long al With Absolute Long al addressing the second thir...

Page 19: ...k move instructions is also loaded into the Data Bank Register Instruction Opcode dstbnk srcbnk Source Address srcbnk X Reg Dest Address dstbnk Y Reg Increment X and Y MVN or decrement X and Y MVP and decrement C if greater than zero then PC PC 3 3 5 10 Direct Indexed Indirect d x Direct Indexed Indirect d x addressing is often referred to as Indirect X addressing The second byte of the instructio...

Page 20: ...ister and the Y Index Register to form the 16 bit effective address The operand is always in Bank 0 Instruction Opcode offset Direct Register offset direct address Y Reg Operand Address 00 effective address 3 5 13 Direct Indirect Indexed d y Direct Indirect Indexed d y addressing is often referred to as Indirect Y addressing The second byte of the instruction is added to the Direct Register D The ...

Page 21: ...ong d With Direct Indirect Long d addressing the second byte of the instruction is added to the Direct Register to form a pointer to the 24 bit effective address Instruction Opcode offset Direct Register then offset 00 direct address Operand Address direct address 3 5 16 Direct Indirect d With Direct Indirect d addressing the second byte of the instruction is added to the Direct Register to form a...

Page 22: ... are added to the Program Counter which has been updated to point to the opcode of the next instruction With the branch instruction the Program Counter is loaded with the result With the Push Effective Relative instruction the result is stored on the stack The offset is a signed 16 bit quantity in the range from 32768 to 32767 The Program Bank Register is not affected 3 5 21 Program Counter Relati...

Page 23: ...et Stack Pointer then offset Operand Address 00 effective address 3 5 24 Stack Relative Indirect Indexed d s y With Stack Relative Indirect Indexed d s y addressing the second byte of the instruction is added to the Stack Pointer to form a pointer to the low order 16 bit base address in Bank 0 The Data Bank Register contains the high order 8 bits of the base address The effective address is the su...

Page 24: ...Direct Indirect 5 3 4 2 Direct Indirect Indexed d y 5 1 5 1 3 4 2 2 Direct Indirect Indexed Long d y 6 3 4 2 Direct Indirect Long 6 3 4 2 Direct X 4 5 4 3 4 5 2 2 Direct Y 4 4 3 4 2 2 Immediate 2 2 3 2 2 3 Implied 2 2 1 1 Relative 2 1 2 2 2 2 2 Relative Long 3 2 3 Stack 3 7 3 8 1 1 Stack Relative 4 3 2 Stack Relative Indirect Indexed 7 3 2 Notes these are indicated in parentheses 1 Page boundary a...

Page 25: ... PHI2 RESB VDDx0 8 VDD 0 3 VDDx0 8 VDD 0 3 VDDx0 8 VDD 0 3 VDDx0 8 VDD 0 3 VDDx0 8 VDD 0 3 V Vil Input Low Voltage ABORTB BE Data IRQB RDY NMIB PHI2 RESB VSS 0 3 VDDx0 2 VSS 0 3 VDDx0 2 VSS 0 3 VDDx0 2 VSS 0 3 VDDx0 2 VSS 0 3 VDDx0 2 V Ipup RDY Input Pullup Current VIN VDDx0 8 5 20 5 20 5 20 2 10 2 10 A Iin Input Leakage Current Vin 0 4 to 2 4 PHI2 Address Data RWB Off state BE 0 All other inputs ...

Page 26: ...6 IDD mA VDD VOLTS 1MHz Operation 85 C Typical 0 6u processed device With tester loading Core power only Figure 4 1 IDD vs VDD 0 0 0 5 1 0 1 5 2 0 2 5 3 0 3 5 4 0 4 5 5 0 5 5 6 0 0 4 8 VDD VOLTS F Max MHz Typical 0 6µ processed device 85 C 2 6 10 12 14 16 18 20 Figure 4 2 F Max vs VDD ...

Page 27: ...BA7 Hold Time 10 10 10 20 40 nS tBAS BA0 BA7 Setup Time 33 40 40 75 150 nS tACC Access Time 30 70 70 130 365 nS tDHR Read Data Hold Time 10 10 10 20 40 nS tDSR Read Data Setup Time 10 15 20 30 40 nS tMDS Write Data Delay Time 30 40 40 70 140 nS tDHW Write Data Hold Time 10 10 10 20 40 nS tPCS Processor Control Setup Time 10 15 15 30 60 nS tPCH Processor Control Hold Time 10 10 10 20 40 nS tEH E MX...

Page 28: ... VDA VPA READ DATA BA0 BA7 WRITE DATA BA0 BA7 IRQB NMIB RESB RDY tF tPWH tF ABORTB M X E tADS tBAS BA0 BA7 BA0 BA7 WRITE DATA READ DATA tDSR tACC tES tDHR tDHW tPCS tPCH M X X tPCS tEH tES M tEH Figure 4 1 General Timing Diagram 1 Timing measurement points are 50 VDD ...

Page 29: ...al Mode 23 CPY Compare Memory and Index Y 69 SEI Set Interrupt Disable Status 24 DEC Decrement Memory or Accumulator by One 70 STA Store Accumulator in Memory 25 DEX Decrement Index X by One 71 STP Stop the Clock 26 DEY Decrement Index Y by One 72 STX Store Index X in Memory 27 EOR Exclusive OR Memory with Accumulator 73 STY Store Index Y in Memory 28 INC Increment Memory or Accumulator by One 74 ...

Page 30: ...e 00FFF4 5 COP Software 00FFF2 3 Reserved 00FFF0 1 Reserved Table 5 3 Native Mode Vector Locations 16 bit Mode Address Label Function 00FFEE F IRQB Hardware 00FFEC D Reserved 00FFEA B NMIB Hardware 00FFE8 9 ABORTB 00FFE6 7 BRK Software 00FFE4 5 COP Software 00FFE2 3 Reserved 00FFE0 1 Reserved The VP output is low during the two cycles used for vector location access When an interrupt is executed D...

Page 31: ...BIT TXA PHB STY STA STX STA r d x rl d s d d d d i i s a a a al 2 2 6 2 4 3 4 2 3 2 3 2 3 2 2 2 2 1 2 2 2 1 3 1 4 3 4 3 4 3 5 4 BCC STA STA STA STY STA STX STA TYA STA TXS TXY STZ STA STZ STA r d y d d s y d x d x d y d y i a y i i a a x a x al x 2 2 6 2 5 2 7 2 4 2 4 2 4 2 6 2 2 1 5 3 2 1 2 1 4 3 5 3 5 3 5 4 LDY LDA LDX LDA LDY LDA LDX LDA TAY LDA TAX PLB LDY LDA LDX LDA d x d s d d d d i i s a a...

Page 32: ...2C 3C 24 34 89 M M Z BMI Branch if N 0 30 BNE Branch if Z 0 D0 BPL Branch if N 0 10 BRA Branch Always 80 BRK Break Note 2 00 0 1 BRL Branch Long Always 82 BVC Branch if V 0 50 BVS Branch if V 1 70 CLC C 0 18 0 CLD 0 D D8 0 CLI 0 1 58 0 CLV 0 V B8 0 CMP A M CD DD D9 CF DF C5 C3 D5 D2 C7 D3 C1 D1 D7 C9 N Z C COP Co Processor 02 0 1 CPX X M EC E4 E0 N Z C CPY Y M CC C4 C0 N Z C DEC Decrement CE 3A DE...

Page 33: ... PER Mpc rl Mpc rl 1 Ms 1 Ms S 2 S 62 PHA A Ms S 1 S 48 PHB DBR Ms S 1 S 8B PHD D Ms Ms 1 S 2 S 0B PHK PBR Ms S 1 S 4B PHP P Ms S 1 S 08 PHX X Ms S 1 S DA PHY Y Ms S 1 S 5A PLA S 1 S Ms A 68 N Z PLB S 1 S Ms DBR AB N Z PLD S 2 S Ms 1 Ms D 2B N Z PLP S 1 S Ms P 28 N V M X D 1 Z C PLX S 1 S Ms X FA N Z PLY S 1 S Ms Y 7A N Z REP M P P C2 N V M X D 1 Z C ROL C 15 7 6 5 4 3 2 1 0 C 2E 2A 3E 26 36 N Z C...

Page 34: ... TAY A Y AB N Z TCD C D 5B N Z TCS C S 1B TDC D C 7B N Z TRB 1C 14 Z TSB AVM M 0C 04 Z TSC S C 3B N Z TSX S X BA N Z TXA X A 8A N Z TXS X S 9A TXY X Y 9B N Z TYA Y A 98 N Z TYX Y X BB N Z WAI 0 RDY CB WDM No Operation 42 XBA B A EB N Z XCE M Y FB E Notes 1 The following are the definitions of the operational symbols used ADD AND xv Exclusive OR Multiply NOT v OR Subtract 2 Bit immediate N and V fl...

Page 35: ...absolute rl program counter relative long a x absolute indexed with x I implied a y absolute indexed with y s stack al absolute long d direct al x absolute long indexed d x direct indexed with x d s stack relative d y direct indexed with y d s y stack relative indirect indexed d direct indirect a absolute indirect d x direct indexed indirect a x absolute indexed indirect d y direct indirect indexe...

Page 36: ... 0 1 1 0 1 1 1 1 1 0 0 0 0 0 PBR PC PBR PC 1 PBR PC 2 DBR AA DBR AA 1 DBR AA 1 DBR AA 1 DBR AA OpCode AAL AAH Data Low Data High IO Data High Data Low 1 1 1 1 1 1 0 0 2a Absolute Indexed Indirect a x JMP 1 OpCode 3 bytes 6 cycles 1 2 3 4 5 6 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 0 1 1 1 PBR PC PBR PC 1 PBR PC 2 PBR PC 2 PBR AA X PBR AA X 1 PBR NEW PC OpCode AAL AAH IO New PCL New PCH O...

Page 37: ...a 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 1 1 0 0 PBR PC PBR PC 1 PBR PC 2 PBR PC 3 AAB AA X AAB AA X 1 OpCode AAL AAH AAB Data Low Data High 1 1 1 1 1 0 1 0 6a Absolute X a x ADC AND BIT CMP EOR LDA LDY ORA SBC STA STZ 12 OpCodes 3 bytes 4 5 and 6 cycles 4 1 1 2 3 3a 4 4a 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 1 0 0 0 PBR PC PBR PC 1 PBR PC 2 DBR AAH AAL XL DBR AA X DBR AA X 1 OpCode AAL AAH IO ...

Page 38: ... 1 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 9b Block Move Positive forward xyc MVP 1 Op Code N 2 3 bytes Byte 7 cycles C 2 x Source Address y Destination c of bytes to move 1 x y Decrement MVP is used when the destination N 1 start address is higher more Byte positive than the source C 1 start address N Byte Last C 0 000000 1 2 3 4 5 6 7 1 2 3 4 5 6 7 1 2 3 4 5 6 7 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1...

Page 39: ... d ADC AND CMP EOR LDA ORA SBC STA 8 OpCodes 2 bytes 5 6 and 7 cycles 2 1 1 2 2a 3 4 5 5a 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 0 0 0 0 0 PBR PC PBR PC 1 PBR PC 1 0 D DO 0 D DO 1 DBR AA DBR AA 1 OpCode DO IO AAL AAH Data Low Data High 1 1 1 1 1 1 0 1 0 13 Direct Indirect Indexed d y ADC AND CMP EOR LDA ORA SBC STA 8 OpCodes 2 bytes 5 6 7 and 8 cycles 2 4 1 1 2 2a 3 4 4a 5 5a 1 1 1 1 1 1 1 ...

Page 40: ...PBR PC 1 PBR PC 1 0 D DO Y 0 D DO Y 1 OpCode DO IO IO Data Low Data High 1 1 1 1 1 0 1 0 18 Immediate ADC AND BIT CMP CPX CPY EOR LDA LDX LDY ORA REP SEC SEP 14 OpCodes 2 and 3 bytes 2 and 3 cycles 1 8 1 2 2a 1 1 1 1 1 1 1 0 0 1 1 1 PBR PC PBR PC 1 PBR PC 2 OpCode IDL IDH 1 1 1 19a Implied i CLC CLD CLI CLV DEX DEY INX INY NOP SEC SED SEI TAX TAY TCD TCS TDC TSC TSX TXA TXS TXY TYA TYX XCE 25 OpCo...

Page 41: ... 1 1 0 0 0 0 1 1 1 22b Stack s PLA PLB PLD PLP PLX PLY Different than N6502 6 Op Codes 1 byte 4 and 5 cycles 1 1 2 3 4 4a 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 0 0 0 0 PBR PC PBR PC 1 PBR PC 1 0 S 1 0 S 2 OpCode IO IO REG Low REG High 1 1 1 1 1 22c Stack s PHA PHB PHP PHD PHK PHX PHY 7 Op Codes 1 byte 3 and 4 cycles 1 12 1 2 3a 3 1 1 1 1 1 1 1 1 1 0 1 1 1 0 0 0 PBR PC PBR PC 1 0 S 0 S 1 OpCode IO REG Hi...

Page 42: ... PC 1 0 S 1 0 S 2 0 S 3 NEW PBR PC OpCode IO IO New PCL New PCH New PBR Next OpCode 1 1 1 1 1 1 1 22j Stack s BRK COP 2 OpCodes 2 bytes 7 and 8 cycles 3 7 10 10 10 1 2 3 4 5 6 7 8 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 PBR PC PBR PC 1 0 S 0 S 1 0 S 2 0 S 3 16 0 VA 0 VA 1 0 AAV OpCode Signature PBR PCH PCL P AAVL AAVH Next OpCode 1 1 0 0 0 0 1 1 1 23 Stack Relativ...

Page 43: ...contains invalid addresses 5 Add 1 cycle if branch is taken 6 Add 1 cycle if branch is taken across page boundaries in 6502 emulation mode E 1 7 Subtract 1 cycle for 6502 emulation mode E 1 8 Add 1 cycle for REP SEP 9 Wait at cycle 2 for 2 cycles after NMIB or IRQB active input 10 RWB remains high during Reset 11 BRK bit 4 equals 0 in Emulation mode 12 PHP and PLP 13 Some OpCodes shown are compati...

Page 44: ...November 09 2018 44 Clock Bank Address BA0 BA7 E D Q OE 573 or 373 8 8 Data Bus D0 D7 8 PHI2 D0 D7 BA0 BA7 R WB W65C816S CE B DIR A 74x245 Figure 5 1 Bank Address Latching Circuit ...

Page 45: ...acters that can be in a label so long as that upper limit is greater than or equal to six characters An assembler may limit the alphabetic characters to upper case characters if desired If lower case characters are allowed they should be treated as identical to their upper case equivalents Other characters may be allowed in the label so long as their use does not conflict with the coding of operan...

Page 46: ...refixing the constant with a character followed by zero or more of either the decimal digits or the hexadecimal digits A F If lower case letters are allowed in the label field then they shall also be allowed as hexadecimal digits 6 3 3 1 All constants no matter what their format shall provide at least enough precision to specify all values that can be represented by a twenty four bit signed or uns...

Page 47: ...Page d a d al a EXT al Absolute Indexed d x EXT d x Accumulator A a x Implied Addressing no operand a x Direct Indirect d y al x Indexed d y EXT x a y EXT x al y Stack Addressing no operand EXT y Direct Indirect d y Stack Relative d s y Indexed Long d y Indirect Indexed d s y a y a s y al y al s y EXT y EXT s y Direct Indexed d x Block Move d d Indirect d x d a a x d al al x d EXT EXT x a d Direct...

Page 48: ... In cases where the addressing modes is not forced the assembler shall assume that the address is two bytes unless the assembler is able to determine the type of addressing required by context in which case that addressing mode will be used Addresses shall be truncated without error in an addressing mode is forced which does not require the entire value of the address For example LDA 0203 and LDA ...

Page 49: ...nd Z flags valid in decimal mode D 0 after reset interrupt Timing A ABS X ASL LSR ROL with no Page Crossing B Jump Indirect Operand XXFF C Branch Across Page D Decimal Mode 7 cycles 5 cycles and invalid page crossing 4 cycles No add cycles 6 cycles 6 cycles 4 cycles Add 1 cycle 6 cycles 6 cycles 4 cycles Add 1 Cycle 7 cycles 5 cycles 4 cycles No add cycles BRK Vector FFFE F BRK bit 0 on stack if I...

Page 50: ...n a 00YY data fetch when using the W65C02S In contrast indexing from page ZZFFXX may result in ZZ 1 00YY when using the W65C816S 7 4 ABORTB Input 7 4 1 ABORTB should be held low for a period not to exceed one cycle Also if ABORTB is held low during the Abort Interrupt sequence the Abort Interrupt will be aborted It is not recommended to abort the Abort Interrupt The ABORTB internal latch is cleare...

Page 51: ...will always be high logic 1 7 8 3 2 MVP and MVN instructions use the X and Y Index Registers for the memory addresses When in emulation mode the Source and Destination Bank addresses for MVP and MVN can only move data in the range 0000 to 00FF See Programming the 65816 Manual for more information 7 9 Indirect Jumps The JMP a and JML a instructions use the direct Bank for indirect addressing while ...

Page 52: ... the PHI2 clock to all internal circuitry When disabled the PHI2 clock is held in the high state In this case the Data Bus will remain in the data transfer state and the Bank address will not be multiplexed onto the Data Bus Upon executing the STP instruction the RESB signal is the only input which can restart the processor The processor is restarted by enabling the PHI2 clock which occurs on the ...

Page 53: ...ulator is transferred to SH Note that in both the Emulation and Native modes the full 16 bits of the Stack Register are transferred to the A B and C Accumulators regardless of the state of the M bit in the Status Register 7 22 BRK Instruction The BRK instruction for the NMOS 6502 65C02 and 65C816 is actually a 2 byte instruction The NMOS device simply skips the second byte i e doesn t care about t...

Page 54: ...e been removed The outputs are the N channel and P channel output transistors drivers The following inputs if not used must be held in the high state RDY input IRQB MIB BE and ABORTB The timing of the W65C816S core is the same as the W65C816S 9 SOFT CORE RTL MODEL 9 1 W65C816 Synthesizable RTL Code in Verilog HDL The RTL Code Register Transfer Level in Verilog is a synthesizable model The behavior...

Page 55: ...Design Center Inc 2166 East Brown Road Mesa Arizona 85213 USA Phone 480 962 4545 Fax 480 835 6442 Info WesternDesignCenter com www WDC65xx com www WesternDesignCenter com ______________________________________________________________________ WARNING MOS CIRCUITS ARE SUBJECT TO DAMAGE FROM STATIC DISCHARGE Internal static discharge circuits are provided to minimize part damage due to environmental ...

Page 56: ...Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery Lifecycle Information Western Design Center WDC W65C816S6PG 14 W65C816S6TQG 14 ...

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