November 09, 2018
8
INTERUPT
LOGIC
VDD
VSS
ABORTB
IRQB
NMIB
RESB
TIMING
CONT.
RDY
CLOCK
GEN-
ERATOR
PHI2
IN
S
T
R
U
C
T
IO
N
D
E
C
O
D
E
M
IN
T
E
R
M
S
IN
S
T
R
U
C
T
IO
N
D
E
C
O
D
E
S
U
M
O
F
M
IN
T
E
R
M
S
R
E
G
IS
T
E
R
T
R
A
N
S
F
E
R
L
O
G
IC
S
T
S
T
E
M
C
O
N
T
R
O
L
RWB
VPA
VDA
MLB
VPB
E
MX
PROCESSOR
STATUS (P)
(8 BITS)
INSTRUCTION REGISTER
(8 BITS)
IN
T
E
R
N
A
L
D
A
T
A
B
U
S
(
1
6
B
IT
S
)
DATA
LATCH/
PREDECODER
IN
T
E
R
N
A
L
S
P
E
C
IA
L
B
U
S
(
1
6
B
IT
S
)
DATA BANK (DBR)
(8 BITS)
PROG. BANK (PBR)
(8 BITS)
DIRECT (D)
(16 BITS)
PROG. COUNTER
(PC) (16 BITS)
ACCUMULATOR
(C) (16 BITS)
(A) (8 BITS)
(B) (8 BITS)
TRANSFER
SWITCHES
ALU
(16 BITS)
STACK POINTER
(S) (16 BITS)
INDEX Y
(16 BITS)
INDEX X
(16 BITS)
A
D
D
R
E
S
S
B
U
F
F
E
R
(
L
O
W
)
A
D
R
E
S
S
B
U
F
F
E
R
(
H
IG
H
)
D
A
T
A
B
U
S
/B
A
N
K
A
D
D
R
E
S
S
B
U
F
F
E
R
IN
T
E
R
N
A
L
A
D
D
R
E
S
S
B
U
S
(
1
6
B
IT
S
)
A0-A7
A8-A15
D0-D7
BE
Figure 2-1 W65C816S Internal Architecture Simplified Block Diagram
