November 09, 2018
54
8 HARD CORE MODEL
8.1
W65C816 Core Information
The W65C816S core uses the same instruction set as the W65C816S
The only functional difference between the W65C816S and W65C816S core is the RDY pin. The
W65C816S RDY pin is bi-directional utilizing an active pull-up. The W65C816S core RDY
function is split into 2 pins, RDYIN and WAITN. The WAITN output goes low when a WAI
instruction is executed.
The W65C816S core will be a smaller die since the I/O buffers have been removed.
The outputs are the N-channel and P-channel output transistors drivers.
The following inputs, if not used, must be held in the high state: RDY input, IRQB, MIB, BE and
ABORTB.
The timing of the W65C816S core is the same as the W65C816S.
9 SOFT CORE RTL MODEL
9.1
W65C816 Synthesizable RTL-Code in Verilog HDL
The RTL-Code (
R
egister
T
ransfer
L
evel) in Verilog is a synthesizable model. The behavior of this model is
equivalent to the original W65C816S hard core. The W65C816S RTL-Code is available as the core model
and the W65C816S standard chip model. The standard chip model includes the soft core and the buffer
ring in RTL-Code. Synthesizable cores are useful in ASIC design.
