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WM_PRJ_Q2686_PTS_001-010
June 30, 2009
Q2686 Wireless CPU
®
3.6
Main Serial Link (UART1)
A flexible 8-wire serial interface is available, complying with V24 protocol
signalling, but not with V28 (electrical interface) due to a 2.8 volts interface.
The signals are:
•
TX data (CT103/TX)
•
RX data (CT104/RX)
•
Request To Send (~CT105/RTS)
•
Clear To Send (~CT106/CTS)
•
Data Terminal Ready (~CT108-2/DTR)
•
Data Set Ready (~CT107/DSR).
•
Data Carrier Detect (~CT109/DCD)
•
Ring Indicator (CT125/RI).
UART1 interface pin description
See Chapter “3.3 Electrical information for digital I/O” for Open drain, 2V8 and 1V8 voltage
characteristics and for Reset state definition.
*According to PC view
With the Open AT
®
Software Suite v2, when the UART1 service is used, the
whole multiplexed signals become unavailable for other purposes. In the
same way if one or more GPIOs (of this table) are allocated the UART1 service
is unavailable.
Signal
Pin
number
I/O I/O
type
Reset
state
Description
Multiplexed
with
CT103/TXD1* 71 I
2V8 Z Transmit
serial
data
GPIO36
CT104/RXD1* 73 O
2V8
1 Receive
serial
data
GPIO37
~CT105/RTS1* 72 I
2V8
Z Request
To
Send
GPIO38
~CT106/CTS1* 75 O
2V8
Z
Clear To Send
GPIO39
~CT107/DSR1* 74 O
2V8
Z
Data Set Ready
GPIO40
~CT108-
2/DTR1*
76 I
2V8
Z Data
Terminal
Ready
GPIO41
~CT109/DCD1 *
70
O 2V8 Undefined Data Carrier
Detect
GPIO43
~CT125/RI1 *
69
O 2V8 Undefined Ring Indicator
GPIO42
CT102/GND* Shielding
leads
GND Ground
