VMIC VMIVME-3124, Product Manual

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500-003124-000
4-5
4.2.3 Control/Status Register
The Board Control/Status register is an 8-bit read/write register at offset $02
that allows software to control the VMIVME-3124 and also indicates its current status.
Seven of the eight bits provide control and indication functions. Table 4.2.3-1 defines the
contents of this register.
Table 4.2.3-1. Board Control/Status Register Contents
Bit Position Bit Name Function
0
Stop Auto
Scan
0 = Scan All Channels (Default)

1 = Scan Single Channel
1 Max Buffer
0 = 16 Differential Data Registers (Default)

1 = 32 Differential Data Registers
2
2’s
Complement
0 = Binary Data (Default)

1 = two’s complement Data
3 Mode 0 Channel 0 BIT Mode 0
4 Mode 1 Channel 0 BIT Mode 1
5 Mode 2 Channel 0 BIT Mode 2
6 Reserved
7 LED Off
0 = Board LED On (Default)

1 = Board LED Off
Normally, the VMIVME-3124 automatically scans all input channels, continually
converting each successive input. The user may set the Stop Auto Scan bit; however, to
cause the VMIVME-3124 to stop on a single channel. If the Stop Auto Scan bit is set, only
the Data Register pointed to by the Channel Pointer Register is updated, although it will
be updated much faster than usual – approximately every 25

sec. The best way to stop
on a single desired channel is to observe the Channel Pointer Register while auto
scanning. Then set the Stop Auto Scan bit within 25

sec as soon as the desired channel
appears. Auto-scanning proceeds from the current channel as soon as this bit is cleared
again.
The Max Buffer bit is only significant when the hardware is configured for
differential inputs, where it controls whether there are 16 Data Registers (one for each
input) or 32 Data Registers (two for each input). The difference between these two
scanning modes is discussed in detail in the Data Register description (Section 4.2.5).
Tables 4.1-1 (Max Buffer clear) and 4.1-2 (Max Buffer set) detail the differences in the
overall VMIVME-3124 memory map.
If the 2’s Complement bit is set, all information in the Data Registers is in two’s
complement format. This data format is only useful when the inputs are configured as
byplay. In this case, the two’s complement data format causes the Data Registers to
contain values already sign-extended. This saves the programmer from having to convert
the data in the host code.