94
C
VMICPCI-7611 Product Manual
Device Address Definition
The standard PC/AT architecture defines two distinctive types of address spaces for
the devices and peripherals on the CPU board. These spaces have typically been
named Memory address space and I/O address space. The boundaries for these areas
are limited to the number of address bus lines that are physically located on the CPU
board. The VMICPCI-7611 has 32 address bus lines located on the board, thereby
defining the limit of the address space as 4 Gbyte. The standard PC/AT architecture
defines Memory address space from zero to 4 Gbyte and the separate I/O address
space from zero to 64 Kbyte.
ISA Devices
The ISA devices on the VMICPCI-7611 are configured by the BIOS at boot-up and
adhere to the standard PC/AT architecture. They are mapped in I/O address space
within standard addresses and their interrupts are mapped to standard interrupt
control registers. However, all of the ISA devices with the exception of the real-time
clock, keyboard, and programmable timer are relocatable to almost anywhere within
the standard 1 Kbyte of I/O address space. Table C-1 defines the spectrum of
addresses available for reconfiguration of ISA devices.
As previously stated, in the standard PC/AT system, all I/O devices are mapped in
I/O address space. On the VMICPCI-7611, however, the Dynamic Random Access
Memory (DRAM), is addressed in Memory address space. The BIOS places DRAM at
address zero and extends to the physical limit of the on-board DRAM.
Table C-1 ISA Device Mapping Configuration
Device
Memory
Space
I/O Address
Space
PIC Interrupt
Options
Byte Address
Boundary
Default
Floppy
N/A
[0x100 - 0xFF8]
IRQ1 - IRQ15
8
$3F0
Serial Port 1
N/A
[0x100 - 0xFF8]
IRQ1 - IRQ15
8
$3F8
Serial Port 2
N/A
[0x100 - 0xFF8]
IRQ1 - IRQ15
8
$2F8
Real-Time Clock
Nonrelocatable
$070
Keyboard
Nonrelocatable
$060
Auxiliary I/O
N/A
- Primary I/O
[0x000 - 0xFFF]
- Secondary I/O
[0x000 - 0xFFF]
IRQ1,
IRQ3-IRQ15
1
1
Watchdog Timer
0x500-50D
N/A
0xD
$500
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