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VMICPCI-7611 Product Manual
Watchdog Alarm Registers
Register C
contains two Watchdog alarm values. Bits 3 - 0 contain the 0.01 Seconds
value with a range of 0 to 9 in BCD while Bits 7 - 4 contain the 0.1 Seconds value with
a range of 0 to 9 in BCD. This Register has a total range of 0.00 to 0.99 Seconds.
Register D
contains two Watchdog Alarm values. Bits 3 - 0 contain the 1 Second value
with a range of 0 to 9 in BCD while Bits 7 - 4 contain the 10 Seconds value with a range
of 0 to 9 in BCD. This Register has a total range of 00.0 to 99.0 Seconds.
The Watchdog Alarm Registers can be read or written in any order. When a new value
is entered or the Watchdog registers are read, the Watchdog Timer will start counting
down from the entered value. When zero is reached the Watchdog Interrupt Output
will go active. If jumper E7 is loaded, the CPU will reset to a known state, refer to
Figure 4-2 on page 52. The Watchdog Timer count is reinitialized back to the entered
value, the Watchdog flag bit is cleared, and the Watchdog interrupt output is cleared
every time either of the registers are accessed. Periodic accesses to the Watchdog
Timer will prevent the Watchdog Alarm from occurring. If access does not occur, the
alarm will be repetitive. The Watchdog Alarm Register always reads the entered
value. The actual countdown value is internal and not accessible to the user. Writing
zero’s to Registers C and D will disable the Watchdog Alarm feature.
Command Register
Register B is the Command Register. Within this register are mask bits, control bits,
and flag bits. The following paragraphs describe each bit.
Te - Bit 7 Transfer Enable
- This bit enables and disables the tracking of data between
the internal and external registers. When set to a logic zero (0), tracking is disabled
that is the data in the external register is frozen. When set to a logic one (1), tracking is
enabled. This bit must be set to a logic one (1) to allow the external register to be
updated.
Ipsw - Bit 6 Interrupt Switch
- This bit toggles the Interrupt Output between the Time
of Day Alarm and the Watchdog Alarm. When set to a logic zero (0), the Interrupt
Output is from the Watchdog Alarm. When set to a logic one (1), the Interrupt Output
is from the Time of Day Alarm.
Ibh/lo - Bit 5 Reserved
- This bit should be set to a logic low (0).
Pu/lvl - Bit 4 Interrupt Pulse Mode or Level Mode
- This bit determines whether the
Interrupt Output will output as a pulse or a level. When set to a logic zero (0),
Interrupt Output will be a level. When set to a logic one (1), Interrupt Output will be a
pulse. In pulse mode the Interrupt Output will sink current for a minimum of 3 ms.
This bit should be set to a logic one (1).
Wam - Bit 3 Watchdog Alarm Mask
- Enables/Disables the Watchdog Alarm to
Interrupt Output when Ipsw (Bit 6, Interrupt Switch) is set to logic zero (0). When set
to a logic zero (0), Watchdog Alarm Interrupt Output will be enabled. When set to a
logic one (1), Watchdog Alarm Interrupt Output will be disabled.
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